Document
DATA SHEET
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2GB Fully Buffered DIMM
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Specifications
• Density: 2GB • Organization 256M words × 72 bits, 2 ranks • Mounting 18 pieces of 1G bits DDR2 SDRAM sealed in FBGA • Package 240-pin fully buffered, socket type dual in line memory module (FB-DIMM) PCB height: 30.35mm Lead pitch: 1.00mm Advanced Memory Buffer (AMB): 655-ball FCBGA Lead-free (RoHS compliant) • Power supply DDR2 SDRAM: VDD = 1.8V ± 0.1V AMB: VCC = 1.5V + 0.075V/ −0.045V • Data rate: 667Mbps (max.) • Eight internal banks for concurrent operation (components) • Interface: SSTL_18 • Burst lengths (BL): 4, 8 • /CAS Latency (CL): 3, 4, 5 • Precharge: auto precharge option for each burst access • Refresh: auto-refresh, self-refresh • Refresh cycles: 8192 cycles/64ms Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Operating case temperature range TC = 0°C to +95°C
Features
• JEDEC standard Raw Card B Design • Industry Standard Advanced Memory Buffer (AMB) • High-speed differential point-to-point link interface at 1.5V (JEDEC spec) 14 north-bound (NB) high speed serial lanes 10 south-bound (SB) high speed serial lanes • Various features/modes: MemBIST and IBIST test functions Transparent mode and direct access mode for DRAM testing Interface for a thermal sensor and status indicator • Channel error detection and reporting • Automatic DDR2 SDRAM bus and channel calibration • SPD (serial presence detect) with 1piece of 256 byte serial EEPROM Note: Warranty void if removed DIMM heat spreader.
Performance
FB-DIMM System clock frequency 167MHz Speed grade PC2-5300F Peak channel throughput 8.0GByte/s FB-DIMM link data rate 4.0Gbps DDR2 SDRAM Speed Grade DDR2-667 (5-5-5) DDR data rate 667Mbps
Document No. E1090E30 (Ver. 3.0) Date Published December 2007 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2007
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Ordering Information
Part number EBE21FE8ACFT-6E-E DIMM speed grade PC2-5300F Component JEDEC speed bin (CL-tRCD-tRP) DDR2-667 (5-5-5) Mounted devices*
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Mounted AMB* IDT Rev. C1
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EDE1108ACSE-8E-E EDE1108ACSE-6E-E
Notes: 1. Please refer to the EDE1104ACSE, EDE1108ACSE, EDE1116ACSE datasheet (E0975E) for detailed operation part and timing waveforms. 2. Please refer to the following documents for detailed operation part and timing waveforms. Advanced Memory Buffer (AMB) specification FB-DIMM Architecture and Protocol specification
Part Number
E B E 21 F E 8 A C F T - 6E - E
Elpida Memory
Type B: Module
Environment code E: Lead Free (RoHS compliant)
Product Family E: DDR2
DRAM Speed Grade 6E: DDR2-667 (5-5-5)
AMB Device Information T: IDT, Rev.C1 Module Outline F: 240-pin DIMM
Density / Rank 21: 2GB/2-rank Module Type F: Fully Buffered Mono Density E: 1Gbit
Mono Organization 8: x8
Die Rev. (Mono)
Power Supply, Interface A: 1.8V, SSTL_1.8
Data Sheet E1090E30 (Ver. 3.0)
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Advanced Memory Buffer Overview
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The Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification. It supports DDR2 SDRAM main memory. The AMB allows buffering of memory traffic to support large memory capacities. All memory control for the DRAM resides in the host, including memory request initiation, timing, refresh, scrubbing, sparing, configuration access, and power management. The AMB interface is responsible for handling FB-DIMM channel and memory requests to and from the local DIMM and for forwarding requests to other DIMMs on the FB-DIMM channel. The FB-DIMM provides a high memory bandwidth, large capacity channel solution that has a narrow host interface. FB-DIMMs use commodity DRAMs isolated from the channel behind a buffer on the DIMM. The memory capacity is 288 devices per channel and total memory capacity scales with DRAM bit density. The AMB is the buffer that isolates the DRAMs from the channel.
Advanced Memory Buffer Functionality The AMB will perform the following FB-DIMM channel functions. • Supports channel initialization procedures as defined in the initialization chapter of the FB-DIMM Architecture and Protocol Specification to align the clocks and the frame boundaries, verify channel connectivity, and identify AMB DIMM position. • Supports the forwarding of southbound and northbound frames, servicing requests directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging the return data into the northbound frames. • If the AMB resides on the last DIMM in the channel, the AMB initializes northbound frames. • Detects errors on the channel and reports them to the host memory controller. • Support the FB-DIMM configuration register set as defined in the register chapters. • Acts as DRAM memory buffer for all read, write, and configuration accesses addressed to the DIMM. • Provides a read buffer FIFO and a write buffer FIFO. • Supports an SMBus protocol interface for access to the AMB configuration regi.