M1A3P1000

v1.0 www.DataSheet4U.com ProASIC3 Flash Family FPGAs with Optional Soft ARM® Support Features and Benefits High Capacity 15 k to 1 M System Gates Up to 144 kbits of True Dual-Port SRAM Up to 300 User I/Os ® Reprogrammable Flash Technology 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process Live at Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design when Powered Off High Performance 350 MHz System Performance 3.3 V, 66 MHz 64-Bit PCI† Clock Conditioning Circuit (CCC) and PLL† 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation Bank-Selectable I/O Voltages—up to 4 Banks per Chip Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above) I/O Registers on Input, Output, and Enable Paths Hot-Swappable and Cold Sparing I/Os‡ Programmable Output Slew Rate† and Drive Strength Weak Pull-Up/-Down IEEE 1149.1 (JTAG) Boundary Scan Test Pin-Compatible Packages across the ProASIC3 Family Six CCC Blocks, One with an Integrated PLL Configurable Phase-Shift, Multiply/Divide, Capabilities and External Feedback Wide Input Frequency Range (1.5 MHz to 350 MHz) Delay In-System Programming (ISP) and Security Secure ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)† Flash...