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LC74794 Dataheets PDF



Part Number LC74794
Manufacturers Sanyo Semicon Device
Logo Sanyo Semicon Device
Description On-Screen Display Controller LSI
Datasheet LC74794 DatasheetLC74794 Datasheet (PDF)

Ordering number : EN*5557 CMOS LSI LC74794, 74794M On-Screen Display Controller LSI Preliminary Overview The LC74794 and LC74794M are CMOS LSIs for onscreen display, a function that displays characters and patterns on a TV screen under microprocessor control. They feature a built-in PDC/VPS/UDT interface circuit. These LSIs support 12 × 18 dot characters and can display 12 lines by 24 characters of text. Package Dimensions unit: mm 3196-DIP30SD [LC74794] Features • Display format: 24 charact.

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Ordering number : EN*5557 CMOS LSI LC74794, 74794M On-Screen Display Controller LSI Preliminary Overview The LC74794 and LC74794M are CMOS LSIs for onscreen display, a function that displays characters and patterns on a TV screen under microprocessor control. They feature a built-in PDC/VPS/UDT interface circuit. These LSIs support 12 × 18 dot characters and can display 12 lines by 24 characters of text. Package Dimensions unit: mm 3196-DIP30SD [LC74794] Features • Display format: 24 characters by 12 rows (Up to 288 characters) • Character format: 12 (horizontal) × 18 (vertical) dots • Character sizes: Three sizes each in the horizontal and vertical directions • Characters in font: 128 • Initial display positions: 64 horizontal positions and 64 vertical positions • Blinking: Specifiable in character units • Blinking types: Two periods supported: 1.0 second and 0.5 second • Blanking: Over the whole font (12 × 18 dots) • Background color — Background coloring: 8 colors (internal synchronization mode): 4fsc — Background coloring: 6 colors (internal synchronization mode): 2fsc — Blue background only: NTSC • Line background color — Can be set for 3 lines — Line background coloring: 8 colors (internal synchronization mode): 4fsc — Line background coloring: 6 colors (internal synchronization mode): 2fsc • External control input: 8-bit serial input format • On-chip sync separator and AFC circuits • PDC/VPS/UDT interface circuit • Composite video output in the PAL or NTSC format SANYO: DIP30SD unit: mm 3216A-MFP30S [LC74794M] SANYO: MFP30S SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 22897HA (OT)/No. 5557-1/30 LC74794, 74794M Pin Assignment Pin Functions Pin no. 1 2 Pin VSS1 XtalIN XtalOUT (MUTE) Crystal oscillator (MUTE input) Ground Function Ground connection (digital system ground) These pins are used either to connect a crystal and capacitor to form an external crystal oscillator to generate internal synchronizing signals, or to input an external clock signal (2fsc or 4fsc). As a mask option, the XtalOUT pin can be set to function as the MUTE input pin. When the MUTE pin is set low, the video output is held at the pedestal level. (A pull-up resistor is built in so the input has hysteresis characteristics.) Switches the mode between external clock input and crystal oscillator operation. A low level selects crystal oscillator operation and a high level selects external clock input. As a mask option, the CTRL1 input pin can be set to function as the CHABLK (character · border) output. This is a 3-value output. PDC/VPS data output enable input. Data output is enabled by a low-level input. (A pull-up resistor is built in so the input has hysteresis characteristics.) Clock input for PDC/VPS data output (A pull-up resistor is built in so the input has hysteresis characteristics.) PDC/VPS data output (This is either an n-channel open-drain output or a CMOS output.) Outputs the state of the external synchronizing signal presence/absence judgment. Outputs a high level when synchronizing signals are present. Outputs the crystal oscillator clock when CS1 is low and RST is low. (This signal is not output on command resets.) Notes 3 4 CTRL1 Crystal oscillator input switching (CHABLK) (CHABLK output) 5 6 7 CS2 SCLK2 DOUT Enable input 2 Clock input 2 Data output 8 External synchronizing signal judgment SYNCJDG output Continued on next page. No. 5557-2/30 LC74794, 74794M Continued from preceding page. Pin no. 9 Pin CS1 Enable input 1 Function Notes Enable input for OSD serial data input Serial data input is enabled by a low-level input. (A pull-up resistor is built in so the input has hysteresis characteristics.) Serial data clock input (A pull-up resistor is built in so the input has hysteresis characteristics.) Serial data input (A pull-up resistor is built in so the input has hysteresis characteristics.) Composite video signal level adjustment power supply (analog system power supply) The charge pump output. Connect a low-pass filter to this pin. VCO control voltage input Ground (VCO ground) Power supply (+5 V: VCO power supply) Connection for the VCO range adjustment resistor Outputs a low level when PDC/VPS data has been received. Composite video signal output Ground (analog system ground) Composite video signal input SECAM chrominance signal input Power supply (+5 V: digital system power supply) Internal sync separator circuit video signal input Internal sync separator circuit adjustment input Composite synchronizing signal output for the built-in sync separator circuit. Can be switched to function as an output for the signal (high or ST. pulse) due to MOD0 by setting SEL0 high. Inputs the vertical synchronizing signal created by integrating the SEPOUT pin output signal. An integration circuit must be connected to the SEPOUT pin. This pin must be tied to VDD1 if unused. Background color phase adjustment resistor co.


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