IDT88P8344

www.DataSheet4U.com SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0 FEATURES IDT88P8344 Functionality - Low speed to high speed SPI exchange device - Logical port (LP) mapping (SPI-3 <-> SPI-4) tables per direction - Per LP configurable memory allocation - Maskable interrupts for fatal errors - Fragment and burst length configurable per interface: min 16 bytes, max 256 bytes Standard Interfaces - Four OIF SPI-3: 8 or 32 bit, 19.44-133 MHz, 256 address range, 64 concurrently active LPs per interface - One OIF SPI-4 phase 2: 80 - 400 MHz, 256 address range, 256 concurrently active LPs - SPI-4 FIFO status channel options: LVDS full-rate LVTTL eighth-rate - Compatible with Network Processor Streaming Interface (NPSI) NPE-Framer mode of operation - SPI-4 ingress LVDS automatic bit alignment and lane de-skew over the entire frequency range - SPI-4 egress LVDS programmable lane pre-skew 0.1 to 0.3 cycle - IEEE 1149.1 JTAG - Serial or parallel microprocessor interface for control and monitoring Full Suite of Performance Monitoring Counters - Number of packets APPLICATIONS - Number of fragments - Number of errors - Number of bytes Green parts available, see ordering information Ethernet transport SONET / SDH packet transport line cards Broadband aggregation Multi-service switches IP services equipment DESCRIPTION The IDT88P8344 is a SPI (System Packet Interface) Exchange with four SPI3 interfaces and one SPI-4 interface. The data that enter on the low speed int...