ICSSSTV32852

Integrated Circuit Systems, Inc. ICSSSTV32852 www.DataSheet4U.com DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 SSTL_2 compatible data registers Product Features: Differential clock signals Supports SSTL_2 class II specifications on inputs and outputs Low-voltage operation - VDD = 2.3V to 2.7V Available in 114 ball BGA package. Pin Configuration 1 A B C D E F G H J 2 3 4 5 6 Truth Table RESET# L H H H Notes: 1. 1 K L Inputs CLK X or Floating ↑ ↑ L or H CLK# X or Floating ↓ ↓ L or H D X or Floating H L X Q Outputs Q L H L Q0(2) M N P R T U V W 114-Pin Ball BGA H = "High" Signal Level L = "Low" Signal Level ↑ = Transition "Low"-to-"High" ↓ = Transition "High"-to-"Low" X = Don't Care Output level before the indicated steady state input conditions were established. Pin Configuration Assignments A B C D E F G H J K L M N P R T U V W 1 Q2A Q3A Q5A Q7A Q8A Q10A Q12A Q13A Q14A Q17A Q18A Q20A Q22A Q23A Q24A D2 D4 D5 D8 2 Q1A VDDQ Q4A Q6A GND Q9A Q11A VDD Q15A Q16A Q19A VDDQ Q21A VDDQ VDD D1 D3 D7 D9 3 CLK GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND RESET# D6 D10 D11 D12 4 CLK# GND VDDQ GND VDDQ VDDQ GND VDDQ GND VDDQ GND GND VDDQ GND VREF D18 D22 D23 D24 5 Q1B VDDQ Q4B Q6B GND Q9B Q11B VDD Q15B Q16B Q19B VDDQ Q21B VDDQ VDD D13 D15 D19 D21 6 Q2B Q3B Q5B Q7B Q8B Q10B Q12B Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B D14 D16 D17 D20 2. Block Diagr...