CY28410-2

www.DataSheet4U.com CY28410-2 Clock Generator for Intel£ Grantsdale Chipset Features Compliant with Intel£ CK410 Supports Intel P4 and Tejas CPU Selectable CPU frequencies Differential CPU clock pairs 100 MHz differential SRC clocks 96 MHz differential dot clock 48 MHz USB clocks CPU x2 / x3 SRC x6 / x7 PCI x9 REF x1 DOT96 x1 USB_48 x1 33-MHz PCI clock Low-voltage frequency select input I2C support with readback capabilities Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction 3.3V power supply 56-pin SSOP and TSSOP packages Block Diagram XIN XOUT Pin Configuration VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[1:6], SRCC[1:6] VDD_PCI PCIF0/ITP_EN PCIF1 PCIF2 VDD_PCI VDD_48 PCI[0:5] USB_48 VDD_PCIF PCIF[0:2] VSS_48 DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T VTT_PWRGD#/PD DOT96C FS_A USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4-SATAT SRC4_SATAC VDD_SRC VDD_REF REF XTAL OSC PLL1 PLL Ref Freq Divider Network FS_[C:A] VTT_PWRGD# IREF PD PLL2 SDATA SCLK I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2 PCI1 PCI0 FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC SRCT6 SRCC6 SRCT5 SRCC5 VSS_SRC 56 SSOP/TSSOP CY28410 ...