74LVC3G34

74LVC3G34 Triple buffer Rev. 05 — 5 October 2007 www.DataSheet4U.com Product data sheet 1. General description The 74LVC3G34 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features I I I I Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: N JESD8-7 (1.65 V to 1.95 V) N JESD8-5 (2.3 V to 2.7 V) N JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 200 V ±24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C. I I I I I I I NXP Semiconductors 74LVC3G34 www.DataSheet4U.com Triple buffer 3. Ordering information Table 1. Ordering information Package Temperature range Name 74LVC3G34DP 74LVC3G34DC 74LVC3G34GT 74LVC3G34GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number VSSOP8 plas...