ICS843002-31

PRELIMINARY Integrated Circuit Systems, Inc. ICS843002-31 www.DataSheet4U.com 700MHZ FEMTOCLOCKS™ VCXO BASED FREQUENCY TRANSLATOR AND JITTER ATTENUATOR FEATURES Outputs: Two high frequency differential LVPECL outputs Output frequency: up to 700MHz One LVCMOS/LVTTL VCXO PLL output with output enable One Reference clock output with output enable One LOCK detect output Input mux supports 3 selectable inputs: one differential input pair and two LVCMOS/LVTTL input clocks 13-bit VCXO PLL feedback and reference dividers provide wide range of frequency translation ratio options FemtoClock frequency multiplier supports rate of: 560MHz - 700MHz ‘Lock Detect’ output reports lock status of VCXO PLL VCXO PLL circuit provides jitter attenuation with loop bandwidth of 250Hz and below (user adjustable) RMS phase jitter, random at 12kHz to 20MHz: <1ps (design target) 3.3V supply voltage 0°C to 70°C ambient operating temperature Industrial temperature information available upon request Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION The ICS843002-31 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from ICS. This monolithic device is a high-performance, PLL-based synchronous clock generator and jitter attenuation circuit. The ICS843002-31 contains two clock multiplication stages that are cascaded in series. The first stage is a VCXO-based PLL that is optimized to provide reference clock ...