ICS843002I-41

www.DataSheet4U.com 700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR ICS843002I-41 Features Two Differential LVPECL outputs Selectable CLKx, nCLKx differential input pairs CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL or single-ended LVCMOS or LVTTL levels Maximum output frequency: 700MHz FemtoClock VCO frequency range: 560MHz - 700MHz RMS phase jitter @ 155.52MHz, using a 19.44MHz crystal (12kHz to 20MHz): 0.81ps (typical) Full 3.3V or mixed 3.3V core/2.5V output operating supply -40°C to 85°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages General Description The ICS843002I-41 is a member of the HiperClockS™ family of high performance clock HiPerClockS™ solutions from IDT. The ICS843002I-41 is a PLL based synchronous clock generator that is optimized for SONET/SDH line card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the 2nd PLL stage (typically 19.44MHz). The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock™VCO. PLL multiplication ratios are selected from internal lookup tables ...