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CXG7003FN Dataheets PDF



Part Number CXG7003FN
Manufacturers Sony Corporation
Logo Sony Corporation
Description Power Amplifier/Antenna Switch Low Noise Down Conversion Mixer
Datasheet CXG7003FN DatasheetCXG7003FN Datasheet (PDF)

CXG7003FN Description The CXG7003FN is a MMIC consisting of the power amplifier, diversity antenna supported switch and low noise down conversion mixer. This IC is designed using the Sony’s GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Diversity antenna supported switch • Small mold package: 26-pin HSOF • Low current consumption: IDD = 150mA (POUT = 20.2d.

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CXG7003FN Description The CXG7003FN is a MMIC consisting of the power amplifier, diversity antenna supported switch and low noise down conversion mixer. This IC is designed using the Sony’s GaAs J-FET process featuring a single positive power supply operation. Features • Operates at a single positive power supply: VDD = 3V • Diversity antenna supported switch • Small mold package: 26-pin HSOF • Low current consumption: IDD = 150mA (POUT = 20.2dBm, f = 1.9GHz) • High power gain: Gp = 40dB Typ. (POUT = 20.2dBm, f = 1.9GHz) • Low current consumption: IDD = 5.5mA Typ. (When no signal) • High conversion gain: Gc = 19.5dB Typ. (f = 1.9GHz) • Low distortion: Input IP3 = –12dBm Typ. (f = 1.9GHz) • High image suppression ratio: IMR = 40dBc Typ. (f = 1.9GHz) • High 1/2 IF suppression ratio: 1/2IFR = 47dBc Typ. (f = 1.9GHz) Applications Digital cordless telephones (PHS) Structure GaAs J-FET MMIC 26 pin HSOF (Plastic) www.DataSheet4U.com Power Amplifier/Antenna Switch + Low Noise Down Conversion Mixer for PHS Absolute Maximum Ratings • Supply voltage VDD • Voltage between gate and source VGSO • Drain current IDD • Allowable power dissipation PD • Control voltage • Supply voltage • Input power 6 1.5 550 3 V V mA W VCTL 6 V VDD PRF 6 10 V dBm • Channel temperature Tch • Operating temperature Topr • Storage temperature Tstg 150 –35 to +85 –65 to +150 °C °C °C Recommended Operating Conditions • Supply voltage VDD • Control voltage (H) • Control voltage (L) 2.7 to 3.3 V VCTL (H) 2.9 to 3.3 VCTL (L) 0 to 0.2 V V Notes on Handling GaAs MMICs are ESD sensitive devices. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E04401-PS CXG7003FN www.DataSheet4U.com Block Diagram and External Circuit 2.2nH PIN 14 13 100pF 15 12 2.2nH VDD1 1nF VDD2 1nF VDD3 10nF 18nH 16 1nF 17 30pF 18 9 100pF 19 8 30pF (RX) 30pF VCTL2 100pF (RFIN) 10nH 6.8nH 23 13pF 24 25 100nF VDD (IF AMP, MIX) 1nF 26 82nH 5pF 1 3 VDD (LO AMP) LOIN 22 10pF 3.9nH 4 13pF 1nF VDD (RF AMP) 5 21 6 20 7 30pF ANT1 ANT2 10 30pF VCTL1 11 1pF (TX) (POUT) VGG 18nH 1.8nH 2 18pF 1nF IFOUT Pin Configuration PIN 14 GND 15 VDD1 16 VDD2 17 VDD3 18 GND 19 RX 20 VCTL2 21 RFIN 22 CAP 23 GND 24 CAP 25 IFOUT/VDD (IF AMP, MIX) 26 13 VGG 12 CAP 11 POUT 10 TX 9 8 7 6 5 4 3 2 1 VCTL1 ANT2 ANT1 GND GND VDD (RF AMP) GND VDD (LO AMP) LOIN –2– CXG7003FN www.DataSheet4U.com Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol LOIN GND GND GND ANT1 ANT2 VCTL1 TX POUT CAP VGG PIN GND VDD1 VDD2 VDD3 GND RX VCTL2 RFIN CAP GND CAP IFOUT/VDD (IF AMP, MIX) Local signal input pin GND pin GND pin GND pin Antenna switch pin. This pin is ANT1-Tx or ANT1-Rx by setting of VCTL1 and VCTL2. Antenna switch pin. This pin is ANT2-Tx or ANT2-Rx by setting of VCTL1 and VCTL2. Antenna switch control 1 pin Tx pin. Signal is input to antenna switch during ANT-Tx. Power amplifier output pin Connection pin of external capacitor (for noise elimination) Gate voltage adjustment pin of power amplifier (first stage, middle stage, rear-end FET) Signal input pin to power amplifier GND pin VDD1 pin of power amplifier (first stage FET) VDD2 pin of power amplifier (middle stage FET) VDD3 pin of power amplifier (rear-end FET) GND pin Rx pin. ANT input signal is output to this pin during ANT1-Rx or ANT2-Rx. Antenna switch control 2 pin RF signal input pin External capacitor connection pin. This pin is connected to LNA FET source. RF amplifier characteristic is optimized during 1.9GHz by the capacitor of 13pF (Typ.). GND pin External capacitor connection pin. IF amplifier distortion is improved by this capacitor. IF output and IF AMP, MIX VDD VDD (LO AMP) VDD pin of local amplifier VDD (RF AMP) VDD pin of RF amplifier Description –3– CXG7003FN www.DataSheet4U.com Electrical Characteristics These specifications are when the Sony's recommended evaluation board shown on page 8 is used. 1. Control Pin Logic for Antenna Switch Conditions of control pins VCTL1 = 3V, VCTL2 = 0V VCTL1 = 0V, VCTL2 = 3V ANT1 – TX ANT2 – RX ON OFF ANT2 – TX ANT1 – RX OFF ON 2. Power Amplifier Block + Antenna Switch Transmitter Block These specifications are common to the ANT1 transmission and ANT2 transmission. Unless otherwise specified: VDD = 3V, IDD = 150mA, POUT = 20.2dBm, f = 1.9GHz When ANT1 transmission: VCTL1 = 3V, VCTL2 = 0V When ANT2 transmission: VCTL1 = 0V, VCTL2 .


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