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LC78626E Dataheets PDF



Part Number LC78626E
Manufacturers Sanyo Semicon Device
Logo Sanyo Semicon Device
Description DSP
Datasheet LC78626E DatasheetLC78626E Datasheet (PDF)

Ordering number : EN5692 CMOS LSI LC78626E DSP for Compact Disk Players Overview The LC78626E is a monolithic compact disk player signal processing and servo control CMOS IC equipped with an internal anti-shock control function. Designed for total functionality including support for EFM-PLL, and one-bit D/A converter, and containing analog low-pass filter, the LC78626E provides optimal cost-performance for low-end CD players that provide anti-shock systems. The basic functions provided by thi.

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Ordering number : EN5692 CMOS LSI LC78626E DSP for Compact Disk Players Overview The LC78626E is a monolithic compact disk player signal processing and servo control CMOS IC equipped with an internal anti-shock control function. Designed for total functionality including support for EFM-PLL, and one-bit D/A converter, and containing analog low-pass filter, the LC78626E provides optimal cost-performance for low-end CD players that provide anti-shock systems. The basic functions provided by this IC include modulation of the EFM signal from the optical pick-up, deinterleaving, detection and correction of signal errors, prevention of a maximum of approximately 10 seconds of skipping, signal processing such as digital filtering (which is useful in reducing the cost of the player), and processing of a variety of servo-related commands from the microprocessor. • After the subcode Q signal passes the CRC check, it is output to the microprocessor through a serial transmission (LSB first). • The demodulated EFM signal is buffered in the internal RAM, which is able to absorb ± 4 frame's worth of jitter resulting from variations in the disk rotation speed. • The demodulated EFM signal is unscrambled to a specific sequence, and deinterleaving is performed. • Error detection and correction is performed, as is a flag process. (C1: two error/C2: two error correction method.) • The C2 flag is set after referencing the C1 flag and the results of the C2 check, where the signal from the C2 flag is interpolated or held at its previous level. The interpolation circuit uses double interpolation. When there are two or more C2 flags in a row, the previous value is held. Continued on next page. Functions • When an HF signal is input, it is sliced to precise levels and converted to an EFM signal. The phase is compared with the internal VCO and a PLL clock is reproduced at an average frequency of 4.3218 MHz. • Precise timing for a variety of required internal timing needs (including the generation of the reference clock) is produced by the attachment of an external 16.9344 MHz crystal oscillator. • The speed of revolution of the disk motor is controlled by the frame phase difference signal generated by the playback clock and the reference clock. • The frame synchronizing signal is detected, stored, and interpolated to insure stable data read back. • The EFM signal is demodulated and converted to 8-bit symbolic data. • The demodulated EFM signal is divided into subcodes and output to the external microprocessor. (Three general I/O ports are shared [exclusively] for this purpose.) Package Dimensions unit: mm 3151-QFP100E (FLP100) [LC78626E] SANYO: QIP100E (FLP100) SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-0005 JAPAN 13098HA(OT) No. 5692-1/32 LC78626E Continued from preceding page. • Command (such as track jump, start focus, disk motor start/stop, muting on/off, track count, etc.) is are executed after they are entered from the microprocessor. (An 8-bit serial input is used.) • The digital output is equipped internally. • High speed access is supported through discretionary track counting. • Using the 4× oversampling digital filter, D/A converter signals with improved continuity of output data are produced. • A ∆∑-type D/A converter using a 3-order noise shaper is equipped internally. (An analog low-pass filter is equipped internally.) • Internal digital attenuator (8-bit-[ALPHA]; 239 steps.) • Internal digital deemphasis. • Uses 0 cross mute. • Bilingual compatibility. • General I/O ports: 4. (Three of these are shared, exclusively, with the subcode output function.) • Up to ten seconds of skip prevention (when using 4M of DRAM) through ADPCM compression/decompression processing. 1M/4M bit DRAM can be selected. • Memory overflow detection output. • Free memory output. Features • 100-pin QFP • A single 3.2 V/5 V power supply No. 5692-2/32 Slice level control Digital out Interpolation mute Equivalent Circuit Block Diagram VCO clock production clock control 2K × 8-bit RAM RAM address generator Sync detect EFM demodulation CLV digital servo ADPCM encoder C1, C2 error detection and correction flag process Digital attenuator Contact detector Shock detector Subcode partition QCRC 4 × oversampling digital filter Data width changer LC78626E Microprocessor interface One-bit DAC ADPCM decoder Overflow process initiation control Servo commands Disable General ports Crystal oscillator-system timing generator Low-pass filter DRAM control No. 5692-3/32 LC78626E Pin Assignment Top view No. 5692-4/32 LC78626E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0V Parameter Maximum power supply voltage Input voltage Output voltage Allowable power dissipation Operating temperature range Storage temperature range Symbol VDD max VIN VOUT Pd max Topr Tstg Conditions Ratings VSS–0.3 to VSS+7.0 VSS–0.3 to VDD+0.3 VSS–0.3 to VDD+0.


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