HYB39S16160AT-8

www.DataSheet4U.com 16 MBit Synchronous DRAM (second generation) Advanced Information High Performance: CAS latency = 3 -8 125 8 7 -10 100 10 8 Units MHz ns ns HYB 39S16400/800/160AT-8/-10 Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Command Data Mask for Read/Write control (× 4, × 8) Dual Data Mask for byte control (× 16) Auto Refresh (CBR) and Self Refresh Suspend Mode and Power Down Mode 4096 refresh cycles/64 ms Random Column Address every CLK (1-N Rule) Single 3.3 V ± 0.3 V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-44-1 400 mil width (× 4, × 8) P-TSOPII-50-1 400 mil width (× 16) fCK tCK3 tAC3 Single Pulsed RAS Interface Fully Synchronous to Positive Clock Edge 0 to 70 °C operating temperature Dual Banks controlled by A11 (Bank Select) Programmable CAS Latency: 1, 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 and full page for Sequential type 1, 2, 4, 8 for Interleave type The HYB 39S1640x/80x/16xAT are dual bank Synchronous DRAM’s based on the die revisions “B” and “C” and organized as 2 banks × 2 MBit × 4, 2 banks × 1 MBit × 8 and 2 banks × 512 kBit × 16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS advanced 16 MBit DR...