Image Sensor. ICX252AQ Datasheet


ICX252AQ Sensor. Datasheet pdf. Equivalent


ICX252AQ


Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor
ICX252AQ
Description The ICX252AQ is a diagonal 8.933mm (Type 1/1.8) interline CCD solid-state image sensor with a square pixel array and 3.24M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/4.28 second. Also, number of vertical pixels decimation allows output of 30 frames per second in high frame rate readout mode. R, G, B primary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology. This chip is suitable for applications such as electronic still cameras, etc. Features • Supports frame readout • High horizontal and vertical resolution • Supports high frame rate readout mode: 30 frames/s, AF1 mode: 60 frames/s, 50 frames/s, AF2 mode: 120 frames/s, 100 frames/s • Square pixel • Horizontal drive frequency: 18MHz • No voltage adjustments (reset gate and substrate bias are not adjusted.) • R, G, B primary color mosaic filters on chip • High sensitivity, low dark current • Continuous variable-speed shutter • Excellent anti-blooming characteristics • Exit pupil distance recommended range –20 to –100mm • 20-pin high-precision plastic package Device Structure • Interline CCD image sensor • Total number of pixels: • Number of effective pixels: • Number of active pixels: • Number of recommended record pixels:...



ICX252AQ
ICX252AQwww.DataSheet4U.com
Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX252AQ is a diagonal 8.933mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 3.24M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/4.28 second.
Also, number of vertical pixels decimation allows
output of 30 frames per second in high frame rate
readout mode.
R, G, B primary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption of
Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, etc.
20 pin DIP (Plastic)
Pin 1
Features
Supports frame readout
High horizontal and vertical resolution
V
Supports high frame rate readout mode: 30 frames/s,
AF1 mode: 60 frames/s, 50 frames/s,
AF2 mode: 120 frames/s, 100 frames/s
Square pixel
4
Horizontal drive frequency: 18MHz
No voltage adjustments (reset gate and substrate bias are not adjusted.)
Pin 11
H
48
R, G, B primary color mosaic filters on chip
High sensitivity, low dark current
Optical black position
Continuous variable-speed shutter
Excellent anti-blooming characteristics
(Top View)
Exit pupil distance recommended range –20 to –100mm
20-pin high-precision plastic package
2
8
Device Structure
Interline CCD image sensor
Total number of pixels:
2140 (H) × 1560 (V) approx. 3.34M pixels
Number of effective pixels:
2088 (H) × 1550 (V) approx. 3.24M pixels
Number of active pixels:
2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm
Number of recommended record pixels: 2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm
aspect ratio 4:3
Chip size:
8.10mm (H) × 6.64mm (V)
Unit cell size:
3.45µm (H) × 3.45µm (V)
Optical black:
Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
Number of dummy bits:
Horizontal 28
Vertical 1 (even fields only)
Substrate material:
Silicon
Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00109-PS

ICX252AQ
Block Diagram and Pin Configuration
(Top View)
10 9 8 7 6 5 4 3 2 1
ICX252AQ
www.DataSheet4U.com
Gb B Gb
R Gr R
Gb B Gb
R Gr R
Gb B Gb
R Gr R
Horizontal register
B
Gr
B
Gr
B
Gr Note)
Note)
: Photo sensor
11 12 13 14 15 16 17 18 19 20
Pin Description
Pin No. Symbol
Description
Pin No. Symbol
Description
1 Vφ4
Vertical register transfer clock
11 VDD
Supply voltage
2 Vφ3A Vertical register transfer clock
12 φRG Reset gate clock
3 Vφ3B Vertical register transfer clock
13 Hφ2
Horizontal register transfer clock
4 Vφ2
Vertical register transfer clock
14 Hφ1
Horizontal register transfer clock
5 Vφ1A Vertical register transfer clock
15 GND GND
6 Vφ1B Vertical register transfer clock
7 TEST Test pin1
8 TEST Test pin1
16 φSUB Substrate clock
17 CSUB Substrate bias2
18 VL
Protective transistor bias
9 GND GND
19 Hφ1
Horizontal register transfer clock
10 VOUT Signal output
20 Hφ2
Horizontal register transfer clock
1 Leave this pin open.
2 DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
–2–




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