Single Positive Edge-triggered D-type Flip Flop
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RD74LVC1G79
Single Positive Edge-triggered D-type Flip Flop
REJ03D0695–0100 Rev.1.00 Feb 23, 2006
...
Description
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RD74LVC1G79
Single Positive Edge-triggered D-type Flip Flop
REJ03D0695–0100 Rev.1.00 Feb 23, 2006
Description
The RD74LVC1G79 has D-type flip flop in a 5-pin package. The input data is transferred to the output at the rising edge of clock pulse CLK. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
The basic gate function is lined up as Renesas uni logic series. Supply voltage range: 1.65 to 5.5 V Operating temperature range: –40 to +85°C All inputs: VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs: VO (Max.) = 5.5 V (@VCC = 0 V) Output current: ±4 mA (@VCC = 1.65 V) ±8 mA (@VCC = 2.3 V) ±24 mA (@VCC = 3.0 V) ±32 mA (@VCC = 4.5 V) Ordering Information
Part Name RD74LVC1G79WPE Package Type WCSP-5 pin Package Code (Previous Code) SXBG0005LB–A (TBS-5CV) Package Abbreviation WP Taping Abbreviation (Quantity) E (3,000 pcs/reel)
Article Indication
Marking Year code Month code
EFYM
Rev.1.00 Feb 23, 2006 page 1 of 6
RD74LVC1G79
Function Table
Inputs CLK ↑ ↑ L H: L: X: ↑: Q0 : High level Low level Immaterial Low to high transition Level of Q before the indicated steady input conditions was established. D H L X
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Output Q H L Q0
Pin Arrangement
0.7 mm Height 0.4 mm 0.4 mm pitch 0.17 mm 5–Ball (WP) GND
3
4
Q
CLK
2
1.1 mm
Pin#1 INDEX
D
1
5
VCC
(Bottom view)
(Top view)
Logic Diagram
CL...
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