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HYB18T256400BFL Dataheets PDF



Part Number HYB18T256400BFL
Manufacturers Qimonda
Logo Qimonda
Description 256-Mbit Double-Data-Rate-Two SDRAM
Datasheet HYB18T256400BFL DatasheetHYB18T256400BFL Datasheet (PDF)

July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History: 2007-07, Rev. 1.11 Page All All Subjects (major changes since last revision) A.

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July 2007 www.DataSheet4U.com HY[B/I]18T256400B[C/F](L) HY[B/I]18T256800B[C/F](L) HY[B/I]18T256160B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM DDR2 SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.11 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM HY[B/I]18T256400B[C/F](L), HY[B/I]18T256800B[C/F](L), HY[B/I]18T256160B[C/F](L) Revision History: 2007-07, Rev. 1.11 Page All All Subjects (major changes since last revision) Adapted Internet edition. Editorial change Added product types with industrial temperature Previous Revision: 2006-12, Rev. 1.00 Previous Revision: 2007-05, Rev. 1.10 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 11172006-LBIU-F1TN 2 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family and describes its main characteristics. 1.1 Features The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Off-Chip-Driver impedance adjustment (OCD) and • 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O On-Die-Termination (ODT) for better signal quality • DRAM organizations with 4, 8 and 16 data in/outputs • Auto-Precharge operation for read and write bursts • Double Data Rate architecture: two data transfers per • Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes • Programmable CAS Latency: 3, 4, 5 and 6 • Average Refresh Period 7.8 μs at a TCASE lower than • Programmable Burst Length: 4 and 8 85 °C, 3.9 μs between 85 °C and 95 °C • Differential clock inputs (CK and CK) • Programmable self refresh rate via EMRS2 setting • Programmable partial array refresh via EMRS2 settings • Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read • DCC enabling via EMRS2 setting • Full and reduced Strength Data-Output Drivers data and center-aligned with write data. • 1K page size • DLL aligns DQ and DQS transitions with clock • Packages: P(G)-TFBGA-60 for ×4 & ×8 components, • DQS can be disabled for single-ended data strobe operation P(G)-TFBGA-84 for ×16 components • RoHS Compliant Products1) • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS • All Speed grades faster than DDR2–400 comply with DDR2–400 timing specifications when run at a clock rate • Data masks (DM) for write data • Posted CAS by programmable additive latency for better of 200 MHz. command and data bus efficiency TABLE 1 Performance Tables for –25(F) Product Type Speed Code Speed Grade Max. Clock Frequency @CL6 @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time –25F DDR2–800D 5–5–5 –2.5 DDR2–800E 6–6–6 400 333 266 200 15 15 45 60 Unit — MHz MHz MHz MHz ns ns ns ns fCK6 fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 400 400 266 200 12.5 12.5 45 57.5 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.11, 2007-07 11172006-LBIU-F1TN 3 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM TABLE 2 Performance Table for –3(S) Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time –3 DDR2–667C 4–4–4 –3S DDR2–667D 5–5–5 333 266 200 15 15 45 60 Unit — MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 333 333 200 12 12 45 57 TABLE 3 Performance table for –3.7 Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time –3.7 DDR2–533C 4–4–4 Unit — MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 266 266 200 15 15 45 60 TABLE 4 Performance Table for –5 Product Type Speed Code Speed Grade Max. Clock Frequency @CL5 @CL4 @CL3 Min. RAS-CAS-Delay Min. Row Precharge Time Min. Row Active Time Min. Row Cycle Time –5 DDR2–400B 3–3–3 Units — MHz MHz MHz ns ns ns ns fCK5 fCK4 fCK3 tRCD tRP tRAS tRC 200 200 200 15 15 40 55 Rev. 1.11, 2007-07 11172006-LBIU-F1TN 4 Internet Data Sheet www.DataSheet4U.com HY[B/I]18T256[40/80/16]0B[C/F](L) 256-Mbit Double-Data-Rate-Two SDRAM 1.2 Description All of the control a.


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