DatasheetsPDF.com

IS41LV4100

Integrated Silicon Solution

1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

IS41C4100 IS41LV4100 1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES • TTL compatible inputs and outputs • Ref...



IS41LV4100

Integrated Silicon Solution


Octopart Stock #: O-671317

Findchips Stock #: 671317-F

Web ViewView IS41LV4100 Datasheet

File DownloadDownload IS41LV4100 PDF File







Description
IS41C4100 IS41LV4100 1Meg x 4 (4-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES TTL compatible inputs and outputs Refresh Interval: 1024 cycles/16 ms Refresh Mode : RAS-Only, CAS-before-RAS (CBR), and Hidden JEDEC standard pinout Single power supply 5V ± 10% (IS41C4100) 3.3V ± 10% (IS41LV4100) Industrail Temperature Range -40oC to 85oC www.DataSheet4U.com ISSI ® PRELIMINARY INFORMATION SEPTEMBER 2001 DESCRIPTION The ISSI IS41C4100 and IS41LV4100 are 1,048,576 x 4-bit high-performance CMOS Dynamic Random Access Memory. Both products offer accelerated cycle access EDO Page Mode. EDO Page Mode allows 512 random accesses within a single row with access cycle time as short as 10ns per 4-bit word. These features make the IS41C4100 and IS41LV4100 ideally suited for high band-width graphics, digital signal processing, high-performance computing systems, and peripheral applications. The IS41C4100 and IS41LV4100 are available in a 20-pin, 300-mil SOJ package. KEY TIMING PARAMETERS Parameter Max. RAS Access Time (tRAC) Max. CAS Access Time (tCAC) Max. Column Address Access Time (tAA) Min. Fast Page Mode Cycle Time (tPC) Min. Read/Write Cycle Time (tRC) -35 35 10 18 12 60 -60 60 15 30 25 110 Unit ns ns ns ns ns PIN CONFIGURATION 20-Pin SOJ I/O0 I/O1 WE RAS A9 1 2 3 4 5 20 19 18 17 16 GND I/O3 I/O2 CAS OE PIN DESCRIPTIONS A0-A9 I/O0-I/O3 WE OE RAS CAS VCC GND NC Address Inputs Data Inputs/Outputs Write Enable Output Enable Row Address Strobe Column Address Strobe Po...




Similar Datasheet




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)