Document
ATF-521P8
High Linearity Enhancement Mode Pseudomorphic HEMT in 2x2 mm2 LPCC[3] Package
[1]
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Data Sheet
Description
Avago Technologies’ ATF‑521P8 is a single-voltage high linearity, low noise E‑pHEMT housed in an 8-lead JEDECstandard leadless plastic chip carrier (LPCC[3]) package. The device is ideal as a medium-power, high-linearity amplifier. Its operating frequency range is from 50 MHz to 6 GHz. The thermally efficient package measures only 2mm x 2mm x 0.75mm. Its backside metalization provides ex‑ cellent thermal dissipation as well as visual evidence of solder reflow. The device has a Point MTTF of over 300 years at a mounting temperature of +85°C. All devices are 100% RF & DC tested.
Features
• Single voltage operation • High linearity and P1dB • Low noise figure • Excellent uniformity in product specifications • Small package size: 2.0 x 2.0 x 0.75 mm3 • Point MTTF > 300 years[2] • MSL-1 and lead-free • Tape-and-reel packaging option available
Specifications
• 2 GHz; 4.5V, 200 mA (Typ.) • 42 dBm output IP3 • 26.5 dBm output power at 1 dB gain compression • 1.5 dB noise figure • 17 dB Gain • 12.5 dB LFOM[4]
Pin Connections and Package Marking
Pin 8 Pin 7 (Drain) Pin 6 Pin 5
Source (Thermal/RF Gnd)
Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source)
Bottom View
Pin 1 (Source) Pin 2 (Gate) Pin 3 Pin 4 (Source) Pin 8
Applications
• Front-end LNA Q2 and Q3, driver or pre-driver amplifier for Cellular/PCS and WCDMA wireless infrastructure • Driver amplifier for WLAN, WLL/RLL and MMDS applica‑ tions • General purpose discrete E-pHEMT for other high linear‑ ity applications
2Px
Top View
Pin 7 (Drain) Pin 6 Pin 5
Note: Package marking provides orientation and identification “2P” = Device Code “x” = Month code indicates the month of manufacture.
Note: 1. Enhancement mode technology employs a single positive Vgs, eliminating the need of negative gate voltage associated with conventional depletion mode devices. 2. Refer to reliability datasheet for detailed MTTF data 3. Conform to JEDEC reference outline MO229 for DRP-N 4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC bias power.
Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model (Class A) ESD Human Body Model (Class 1C) Refer to Avago Technologies Application Note A004R: Electrostatic Discharge Damage and Control.
ATF-521P8 Absolute Maximum Ratings [1]
Symbol VDS VGS VGD I
DS
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Parameter
Units V V V mA mA
[3]
Absolute Maximum 7 -5 to 1 -5 to 1 500 46 1.5 27 150 -65 to 150 45
Drain – Source Voltage [2] Gate –Source Voltage Gate Drain Voltage [2] Drain Current
[2] [2]
IGS P
diss
Gate Current Total Power Dissipation RF Input Power Channel Temperature Storage Temperature Thermal Resistance
[4]
W dBm °C °C °C/W
Pin max. TCH TSTG θch_b
Notes: 1. Operation of this device in excess of any one of these parameters may cause permanent damage. 2. Assumes DC quiescent conditions. 3. Board (package belly) temperatureTB is 25°C. Derate 22 mW/°C for TB > 83°C. 4. Channel to board thermal resistance measured using 150°C Liquid Crystal Measurement method. 5. Device can safely handle +27dBm RF Input Power provided IGS is limited to 46mA. IGS at P1dB drive level is bias circuit dependent.
Product Consistency Distribution Charts [5, 6]
600 500 400
IDS (mA)
0.8V 0.7V
180 150 120 90
Vgs = 0.6V
Stdev = 0.19
150 Cpk = 0.86 Stdev = 1.32 120
300 200 100 0
-3 Std
+3 Std
90
-3 Std
+3 Std
60 60 30 0 6 8 30
0.5V 0.4V
0
2
4 VDS (V)
0
0.5
1
1.5 NF (dB)
2
2.5
3
0
37
39
41
43 OIP3 (dBm)
45
47
49
Figure 1. Typical I-V Curves. (VGS = 0.1 V per step)
180 150 120 90 60 30 0 -3 Std +3 Std Cpk = 2.13 Stdev = 0.21
Figure 2. NF @ 2 GHz, 4.5 V, 200 mA. Nominal = 1.5 dB.
300 250 200 150 100 50 0 -3 Std +3 Std
Figure 3. OIP3 @ 2 GHz, 4.5 V, 200 mA. Nominal = 41.9 dBm, LSL = 38.5 dBm.
Cpk = 4.6 Stdev = 0.11
15
16
17 GAIN (dB)
18
19
25
25.5
26
26.5
27
27.5
P1dB (dBm)
Figure 4. Gain @ 2 GHz, 4.5 V, 200 mA. Nominal = 17.2 dB, LSL = 15.5 dB, USL = 18.5 dB.
Figure 5. P1dB @ 2 GHz, 4.5 V, 200 mA. Nominal = 26.5 dBm, LSL = 25 dBm.
Notes: 5. Distribution data sample size is 500 samples taken from 5 different wafers. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 6. Measurements are made on production test board, which represents a trade-off between optimal OIP3, P1dB and VSWR. Circuit losses have been de‑embedded from actual measurements.
ATF-521P8 Electrical Specifications
TA = 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise specified. Symbol Parameter and Test Condition Units Min.
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Typ.
Max.
— — — — — — — 18.5 — — — — —
Vgs Operational Gate Voltage Vds = 4.5V, Ids = 200 mA V — 0.62 Vth Threshold .