DatasheetsPDF.com

EMIF02-MIC02F3 Dataheets PDF



Part Number EMIF02-MIC02F3
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description EMI filter including ESD protection
Datasheet EMIF02-MIC02F3 DatasheetEMIF02-MIC02F3 Datasheet (PDF)

EMIF02-MIC02F3 2-line IPAD™, EMI filter including ESD protection Features ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency EMI filtering ■ Lead-free package ■ Very low PCB space consumption: 0.9 mm2 ■ Very thin package: 0.60 mm ■ High efficiency ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging Complies with the following standards ■ IEC61000-4-2 level 4 on external pins: – 15 kV (ai.

  EMIF02-MIC02F3   EMIF02-MIC02F3


Document
EMIF02-MIC02F3 2-line IPAD™, EMI filter including ESD protection Features ■ EMI symmetrical (I/O) low-pass filter ■ High efficiency EMI filtering ■ Lead-free package ■ Very low PCB space consumption: 0.9 mm2 ■ Very thin package: 0.60 mm ■ High efficiency ESD suppression ■ High reliability offered by monolithic integration ■ High reduction of parasitic elements through integration and wafer level packaging Complies with the following standards ■ IEC61000-4-2 level 4 on external pins: – 15 kV (air discharge) – 8 kV (contact discharge) ■ IEC61000-4-2 level 1 on internal pins: – 2 kV (air discharge) – 2 kV (contact discharge) Applications Where EMI filtering in ESD sensitive equipment is required: ■ Mobile phones and communication systems ■ Computers, printers and MCU Boards Description The EMIF02-MIC02F3 is a highly integrated device designed to suppress EMI/RFI noise in all systems subjected to electromagnetic interference. This filter includes ESD protection circuitry, which prevents damage to the protected device when subjected to ESD surges up 15 kV. Flip Chip (6 bumps) Figure 1. Pin layout (bump side) 32 1 E2 GND E1 A I2 GND I1 B Figure 2. Basic cell configuration Low-pass Filter I1 E1 I2 E2 GND GND GND Ri/o = 470 Ω Cline = 16 pF April 2008 TM: IPAD is a trademark of STMicroelectronics. Rev 2 1/8 www.st.com Characteristics 1 Characteristics EMIF02-MIC02F3 Table 1. Absolute ratings (limiting values) Symbol Parameter External pins (A1, A3): ESD discharge IEC61000-4-2, air discharge VPP ESD discharge IEC61000-4-2, contact discharge Internal pins (B1, B3): ESD discharge IEC61000-4-2, air discharge ESD discharge IEC61000-4-2, contact discharge Tj Junction temperature Top Operating temperature range Tstg Storage temperature range Value Unit 15 8 kV 2 2 125 °C -40 to + 85 °C -55 to 150 °C Table 2. Symbol VBR IRM VRM VCL Rd IPP RI/O Cline Electrical characteristics (Tamb = 25 °C) Parameters Breakdown voltage Leakage current @ VRM Stand-off voltage Clamping voltage Dynamic impedance Peak pulse current Series resistance between Input & Output VCL VBR VRM Input capacitance per line I IPP IR IRM IRM VRM VBR VCL V IR IPP Symbol Test conditions VBR IRM RI/O Cline IR = 1 mA VRM = 12 V per line Tolerance ± 10 % Vline = 0V, VOSC = 30 mV, F = 1 MHz, (measured under zero light conditions) Min Typ Max Unit 14 16 V 200 nA 470 Ω 16 20 pF 2/8 EMIF02-MIC02F3 Characteristics Figure 3. S21 (dB) attenuation measurement Figure 4. (Line 1) dB 0.00 dB 0.00 S21 (dB) attenuation measurement (Line 2) -10.00 -10.00 -20.00 -20.00 -30.00 -30.00 -40.00 -40.00 -50.00 -60.00 100.0k 1.0M Line 1 f (Hz) 10.0M 100.0M 1.0G -50.00 -60.00 100.0k 1.0M Line 2 f (Hz) 10.0M 100.0M 1.0G Figure 5. Analog crosstalk measurement dB 0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 100.0k 1.0M Xtalk 1/2 f (Hz) 10.0M 100.0M 1.0G Figure 6. Digital crosstalk measurement Output Line 2 10mV/d Input Line 1 1V/d 10ns/d 5Gs/s Figure 7. ESD response to IEC 61000-4-2 Figure 8. (+15 kV air discharge) on one input and on one output ESD response to IEC 61000-4-2 (-15 kV air discharge) on one input and on one output Input 20V/d Input 20V/d Output 10V/d 100ns/d Output 10V/d 100ns/d 3/8 Application information EMIF02-MIC02F3 Figure 9. Line capacitance versus applied voltage 18 CLINE (pF) 16 14 12 10 8 6 4 2 VLINE (V) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 2 Application information Figure 10. Aplac model E1 Rbump Lbump Rline Lbump Rbump I1 MODEL = D1 MODEL = D2 MODEL = D1 E2 Rbump Lbump Rline MODEL = D3 MODEL = D2 I2 Lbump Rbump Ls Rs E1 I1 Rs Ls Port1 50 Port2 50 Lbump Rbump Lbump Rbump Lgnd Rgnd Lgnd Rgnd Figure 11. Aplac parameters Variables aplacvar Rline 490 aplacvar C_d1 11p aplacvar C_d2 5p aplacvar C_d3 240p aplacvar L 2pH aplacvar Ls 950pH aplacvar Rs 150m aplacvar Lbump 50pH aplacvar Rbump 20m aplacvar Lgnd 80pH aplacvar Rgnd 100m Diode D1 BV=7 CJO=c_d1 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.85 VJ=0.6 TT=50n Diode D2 BV=7 CJO=c_d2 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.85 VJ=0.6 TT=50n Diode D3 BV=7 CJO=c_d3 IBV=1u IKF=1000 IS=10f ISR=100p N=1 M=0.3333 RS=0.47 VJ=0.6 TT=50n 4/8 EMIF02-MIC02F3 3 Ordering information scheme Ordering information scheme Figure 12. Ordering information scheme EMIF yy - xxx zz Fx EMI Filter Number of lines Information x = resistance value (Ohms) z = capacitance value / 10(pF) or 3 letters = application 2 digits = version Package F = Flip Chip x = 3: Lead-free, pitch = 400 µm, bump = 255 µm 4 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maxi.


EL5462 EMIF02-MIC02F3 HD61202U


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site.
(Privacy Policy & Contact)