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ADC12DL040 Dataheets PDF



Part Number ADC12DL040
Manufacturers National Semiconductor
Logo National Semiconductor
Description 210mW A/D Converter
Datasheet ADC12DL040 DatasheetADC12DL040 Datasheet (PDF)

November 2005 www.DataSheet4U.com ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter General Description The ADC12DL040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power.

  ADC12DL040   ADC12DL040



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November 2005 www.DataSheet4U.com ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter ADC12DL040 Dual 12-Bit, 40 MSPS, 3V, 210mW A/D Converter General Description The ADC12DL040 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption while providing excellent dynamic performance and a 250 MHz Full Power Bandwidth. Operating on a single +3.0V power supply, the ADC12DL040 achieves 11.1 effective bits at nyquist and consumes just 210 mW at 40 MSPS, including the reference current. The Power Down feature reduces power consumption to 36 mW. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a singleended input. Full use of the differential input is recommended for optimum performance. The digital outputs from the two ADC’s are available on a single multiplexed 12-bit bus or on separate buses. Duty cycle stabilization and output data format are selectable using a quad state function pin. The output data can be set for offset binary or two’s complement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC12DL040 can be connected to a separate supply voltage in the range of 2.4V to the analog supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of −40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Features n n n n n n n Single +3.0V supply operation Internal sample-and-hold Internal reference Outputs 2.4V to 3.6V compatible Power down mode Duty Cycle Stabilizer Multiplexed Output Mode Key Specifications n n n n n n n n Resolution DNL SNR (fIN = 10 MHz) SFDR (fIN = 10 MHz) Data Latency Power Consumption -- Operating -- Power Down Mode 12 Bits ± 0.3 LSB (typ) 69 dB (typ) 85 dB (typ) 7 Clock Cycles 210 mW (typ) 36 mW (typ) Applications n n n n n n n Ultrasound and Imaging Instrumentation Communications Receivers Sonar/Radar xDSL Cable Modems DSP Front Ends Connection Diagram 20100201 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201002 www.national.com ADC12DL040 Ordering Information Industrial (−40˚C ≤ TA ≤ +85˚C) ADC12DL040CIVS ADC12DL040EVAL Package 64 Pin TQFP Evaluation Board www.DataSheet4U.com Block Diagram 20100202 www.national.com 2 ADC12DL040 Pin Descriptions and Equivalent Circuits Pin No. ANALOG I/O 15 2 VINA+ VINB+ Symbol Equivalent Circuit Description www.DataSheet4U.com 16 1 VINA− VINB− Differential analog input pins. With a 1.0V reference voltage the differential full-scale input signal level is 2.0 VP-P with each input pin voltage centered on a common mode voltage, VC.


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