ATU18

www.DataSheet4U.com Features High Performance ULC Family Suitable for Latest CPLDs and FPGAs conversion Very effective associated Physical synthesis/optimization Flow From 45K Gates up to 1000K Gates Supported From 55Kbit to 847Kbit DPRAM Compatible with Xilinx and Altera Latest FPGA’s Pin-count: Over 700 pins VDD 1.8V +/- 0.15V for core; 1.8V, 2.5V, 3.3V for Periphery Any Pin–out Matched Full Range of Packages: PQFP/TQFP/VQFP, BGA/FLBGA, PGA/PPGA, QFN, CS Available in Commercial, Industrial and Military Grades 0.18 um Drawn CMOS, 5 Metal Layers Library Optimised for best Synthesis, Place & route and Testability Generation (ATPG) High system clock Skew Control 250Mhz system clock, up to 400Mhz for local clock Power on Reset, PLL, Multiplier Standard 3, 6, 12, 24 mA I/Os LVCMOS, LVTTL, GTL, HSTL, LVPECL, PCI & LVDS Interfaces High Noise & EMC Immunity Thick Oxide periphery Allowing Interface with 2.5V and 3.3V Environments 0.18 um ULC Series with Embedded DPRAM ATU18 Description The ATU18 series of ULCs are fully suited for conversion of latest CPLDs and FPGAs. It supports within one ULC 55Kbits to 847Kbits DPRAM and 45Kgates to 1000 Kgates. Typically, ULC die size is 50% smaller than the equivalent FPGA. Metal level customisation allows a DPRAM blocks compatibility with Xilinx® or Altera® blocks. Devices are implemented in high–performance 0.18 um CMOS technology to improve the design frequency and reach 250Mhz typical application and ...