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IS61LF51218A

Integrated Silicon Solution

256K x 36-512K x 18 9Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

IS61LF25636A IS61LF51218A IS61VF25636A IS61VF51218A www.DataSheet4U.com ISSI MAY 2005 ® 256K x 36, 512K x 18 9 Mb S...


Integrated Silicon Solution

IS61LF51218A

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Description
IS61LF25636A IS61LF51218A IS61VF25636A IS61VF51218A www.DataSheet4U.com ISSI MAY 2005 ® 256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs and data outputs Auto Power-down during deselect Single cycle deselect Snooze MODE for reduced-power standby JTAG Boundary Scan for PBGA package Power Supply LF: VDD 3.3V + 5%, VDDQ 3.3V/2.5V + 5% VF: VDD 2.5V + 5%, VDDQ 2.5V + 5% JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-pin PBGA packages Lead-free available DESCRIPTION The ISSI IS61LF/VF25636A and IS61LF/VF51218A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LF/ VF25636A is organized as 262,144 words by 36 bits. The IS61LF/VF51218A is organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cyc...




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