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IS64LPS12832A Dataheets PDF



Part Number IS64LPS12832A
Manufacturers Integrated Silicon Solution
Logo Integrated Silicon Solution
Description 4Mb SYNCHRONOUS PIPELINED SINGLE CYCLE DESELECT STATIC RAM
Datasheet IS64LPS12832A DatasheetIS64LPS12832A Datasheet (PDF)

IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and da.

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IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 128K x 32, 128K x 36, 256K x 18 DECEMBER 2013 4 Mb SYNCHRONOUS PIPELINED, Single CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth ex- pansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Single cycle deselect • Snooze MODE for reduced-power standby • Power Supply LPS: Vdd 3.3V + 5%, Vddq 3.3V/2.5V + 5% VPS: Vdd 2.5V + 5%, Vddq 2.5V + 5% • JEDEC 100-Pin QFP, 119-ball and 165-ball BGA packages • Automotive temperature available • Lead Free available FAST ACCESS TIME Symbol Parameter tkq Clock Access Time tkc Cycle Time Frequency DESCRIPTION The  ISSI IS61(64)LPS12832A, IS61(64)LPS/VP- S12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.The IS61(64)LPS12832A is organized as 131,072 words by 32 bits.The IS61(64)LPS/ VPS12836A is organized as 131,072 words by 36 bits. The IS61(64)LPS/VPS25618A is organized as 262,144 words by 18 bits.Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input.Write cycles can be one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating. 250 200 Units 2.6 3.1 ns 4 5 ns 250 200 MHz Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. 1 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A BLOCK DIAGRAM CLK ADV ADSC ADSP A 17/18 MODE CLK Q0 A0 A0' BINARY COUNTER CE Q1 A1 A1' CLR D Q ADDRESS REGISTER CE CLK 15/16 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY 17/18 32, 36, or 18 32, 36, or 18 GW BWE BW(a-d) x18: a,b x32/x36: a-d D DQ(a-d) Q BYTE WRITE REGISTERS CLK CE CE2 CE2 ZZ OE 2 POWER DOWN D Q ENABLE REGISTER CE CLK D Q ENABLE DELAY REGISTER CLK 2/4/8 INPUT REGISTERS CLK OUTPUT REGISTERS CLK 32, 36, or 18 DQa - DQd OE Integrated Silicon Solution, Inc. Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 165-pin BGA 165-Ball, 13x15 mm BGA 1mm Ball Pitch, 11x15 Ball Array 119-pin BGA 119-Ball, 14x22 mm BGA 1mm Ball Pitch, 7x17 Ball Array Bottom view Bottom View Integrated Silicon Solution, Inc. 3 Rev. H1 12/06/2013 IS61(64)LPS12832A IS61(64)LPS12836A IS61(64)VPS12836A IS61(64)LPS25618A IS61(64)VPS25618A 119 BGA PACKAGE PIN CONFIGURATION 128K x 36 (TOP VIEW) 1 2 3 4 A VDDQ A B NC CE2 A ADSP A ADSC C NC A A VDD D DQc DQPc Vss NC E DQc DQc V.


IS64LPS12836A IS64LPS12832A IS64LPS25618A


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