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HYB18T256161BF-25 Dataheets PDF



Part Number HYB18T256161BF-25
Manufacturers Qimonda AG
Logo Qimonda AG
Description 256-Mbit x16 DDR2 SDRAM
Datasheet HYB18T256161BF-25 DatasheetHYB18T256161BF-25 Datasheet (PDF)

June 2007 www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.20 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256161BF–20/25/28 Revision History: 2007-06, Rev. 1.20 Page All All 94-101 82-86 All Subjects (major changes since last revision) Typos corrected Final Data Sheet added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; se.

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June 2007 www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit x16 DDR2 SDRAM DDR2 SDRAM RoHS compliant Internet Data Sheet Rev. 1.20 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256161BF–20/25/28 Revision History: 2007-06, Rev. 1.20 Page All All 94-101 82-86 All Subjects (major changes since last revision) Typos corrected Final Data Sheet added chapter 7 explaining AC timing measurement condition (reference load ; slew rate ; set up & hold timing references ; derating values for input /command ,data ) setup & hold timings are changed with reference to Industrial standard definition removed all the occurances of RDQS as it in not used in graphics (x16) Previous Revision: Rev. 1.0, 2006-09 Previous Revision: Rev. 0.60, 2006-09 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 11232006-QP6X-6EM0 2 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM 1 Overview This chapter gives an overview of the 256-Mbit Double-Data-Rate-Two SDRAM product family for graphics applications and describes its main characteristics. 1.1 Features The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features: • Data masks (DM) for write data • 1.8 V ± 0.1V VDD for [–20/–25/–28] • 1.8 V ± 0.1V VDDQ for [–20/–25/–28] • Posted CAS by programmable additive latency for better • DRAM organizations with 16 data in/outputs command and data bus efficiency • Double Data Rate architecture: • Off-Chip-Driver impedance adjustment (OCD) and On– two data transfers per clock cycle Die-Termination (ODT) for better signal quality. – four internal banks for concurrent operation • Auto-Precharge operation for read and write bursts • Programmable CAS Latency: 3, 4, 5, 6, 7 • Auto-Refresh, Self-Refresh and power saving PowerDown modes • Programmable Burst Length: 4 and 8 • Average Refresh Period 7.8 μs at a TCASE lower than 85°C, • Differential clock inputs (CK and CK) • Bi-directional, differential data strobes (DQS and DQS) are 3.9 μs between 85°C and 95°C transmitted / received with data. Edge aligned with read • Full Strength and reduced Strength (60%) Data-Output Drivers data and center-aligned with write data. • DLL aligns DQ and DQS transitions with clock • 1K page size • Package: P-TFBGA-84 • DQS can be disabled for single-ended data strobe operation • RoHS Compliant Products1) • Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS TABLE 1 Ordering Information for RoHS compliant products Product Number HYB18T256161BF–20/25/28 Org. × 16 Clock (MHz) 500/400/350 Package P-TFBGA-84 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 1.20, 2007-06 11232006-QP6X-6EM0 3 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM 1.2 Description The 256-Mb DDR2 DRAM is a high-speed Double-Data-Rate-Two CMOS Synchronous DRAM device containing 268,435,456 bits and internally configured as a quad bank DRAM. The 256-Mb device is organized as 4 Mbit × 16 I/O × 4 banks chip. These synchronous devices achieve high speed transfer rates starting at 700 Mb/sec/pin for general applications. The device is designed to comply with all DDR2 DRAM key features: 1. posted CAS with additive latency, 2. write latency = read latency - 1, 3. normal and weak strength data-output driver, 4. Off-Chip Driver (OCD) impedance adjustment 5. On-Die Termination (ODT) function. All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion. A 15-bit address bus is used to convey row, column and bank address information in a RAS-CAS multiplexing style. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package. Rev. 1.20, 2007-06 11232006-QP6X-6EM0 4 Internet Data Sheet www.DataSheet4U.com HYB18T256161BF–20/25/28 256-Mbit Double-Data-Rate-Two SDRAM 2 2.1 Configuration Chip Configuration The chip confi.


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