KS8893ML

KS8893M/ML/MI www.DataSheet4U.com Integrated 3-Port 10/100 Managed Switch with PHYs Preliminary Data Sheet Rev. 1.0 General Description The KS8893M, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, tag/port-based VLAN, QoS priority, management, management information base (MIB) counters, MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications. The KS8893M contains two 10/100 transceivers with patented mixed-signal low-power technology, three media access control (MAC) units, a high-speed non-blocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. Both PHY units support 10BASE-T and 100BASETX. In addition, one PHY unit supports 100BASEFX. The KS8893ML is the single power supply version with all the identical rich features of the KS8893M. ___________________________________________________________________________________________________ Functional Diagram 1K LOOK-UP ENGINE FIFO, FLOW CONTROL, VLAN TAGGING, PRIORITY HP AUTO MDIX 10/100 T/TX/FX PHY 1 10/100 T/TX PHY 2 10/100 MAC 1 QUEUE MANAGEMENT HP AUTO MDIX 10/100 MAC 2 BUFFER MANAGEMENT RMII/MII/ SNI 10/100 MAC 3 FRAME BUFFERS SNI SPI SPI MIB COUNTERS MIIM SMI I2C P1 LED[3:0] P2 LED[3:0] CONTROL REGISTERS EEPROM INTERFACE LED DRIVERS STRAP IN CONFIGURATION June 2005 1 M...