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A67L8336

AMIC Technology

512K X 18- 256K X 36 LVTTL / Pipelined ZeBL SRAM

www.DataSheet4U.com A67L9318/A67L8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revi...


AMIC Technology

A67L8336

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www.DataSheet4U.com A67L9318/A67L8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev. No. 0.0 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.0) AMIC Technology, Corp. www.DataSheet4U.com A67L9318/A67L8336 Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM General Description The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67L9318, A67L8336 SRAMs integrate a 512K X 18, 256K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive...




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