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PMWD15UN

NXP Semiconductors

Dual N-channel uTrenchMOS ultra low level FET

PMWD15UN Rev. 04 — 5 April 2005 www.DataSheet4U.com Dual N-channel µTrenchMOS™ ultra low level FET Product data sheet ...


NXP Semiconductors

PMWD15UN

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PMWD15UN Rev. 04 — 5 April 2005 www.DataSheet4U.com Dual N-channel µTrenchMOS™ ultra low level FET Product data sheet 1. Product profile 1.1 General description Dual common drain N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology. 1.2 Features s Surface mounting package s Very low threshold voltage s Low profile s Fast switching 1.3 Applications s Portable appliances s Battery management s PCMCIA cards s Load switching 1.4 Quick reference data s VDS ≤ 20 V s Ptot ≤ 4.2 W s ID ≤ 11.6 A s RDSon ≤ 18.5 mΩ 2. Pinning information Table 1: Pin 1, 8 2, 3 4 5 6, 7 Pinning Description drain (D) source1 (S1) gate1 (G1) gate2 (G2) source2 (S2) G1 S1 G2 S2 mbl600 Simplified outline 8 5 Symbol D D 1 4 SOT530-1 (TSSOP8) Philips Semiconductors PMWD15UN Dual N-channel µTrenchMOS™ ultra low level FET w w w . D a t a S h e e t 4 U . c 3. Ordering information Table 2: Ordering information Package Name PMWD15UN TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 4.4 mm Version SOT530-1 Type number 4. Limiting values Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM [1] Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 Tsp = 100 °C; VGS = 4.5 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1 [1] [1] [1] [1] Min −55 −55 [...




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