Document
PMWD16UN
Rev. 02 — 24 March 2005
www.DataSheet4U.com
Dual N-channel µTrenchMOS™ ultra low level FET
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS™ technology.
1.2 Features
s Surface mounting package s Very low threshold voltage s Low profile s Fast switching
1.3 Applications
s Portable appliances s Battery management s PCMCIA cards s Load switching
1.4 Quick reference data
s VDS ≤ 20 V s Ptot ≤ 3.1 W s ID ≤ 9.9 A s RDSon ≤ 19 mΩ
2. Pinning information
Table 1: Pin 1 2, 3 4 5 6, 7 8 Pinning Description drain1 (D1) source1 (S1) gate1 (G1) gate2 (G2) source2 (S2) drain2 (D2)
1 4
S1 G1 S2 G2
msd901
Simplified outline
8 5
Symbol
D1
D2
SOT530-1 (TSSOP8)
Philips Semiconductors
PMWD16UN
Dual N-channel µTrenchMOS™ ultra low level FET
w w w . D a t a S h e e t 4 U . c
3. Ordering information
Table 2: Ordering information Package Name PMWD16UN TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 4.4 mm Version SOT530-1 Type number
4. Limiting values
Table 3: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM
[1]
Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Tsp = 25 °C; VGS = 4.5 V; Figure 2 and 3 Tsp = 100 °C; VGS = 4.5 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1
[1] [1] [1] [1]
Min −55 −55
[1] [1]
Max 20 20 ±10 9.9 5.9 39.5 3.1 +150 +150 2.6 10
Unit V V V A A A W °C °C A A
drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage drain current (DC) peak drain current total power dissipation storage temperature junction temperature
Source-drain diode source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs
Single device conducting.
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9397 750 14724
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 24 March 2005
2 of 12
Philips Semiconductors
PMWD16UN
www.DataSheet4U.com
Dual N-channel µTrenchMOS™ ultra low level FET
120 Pder (%) 80
03aa17
120 Ider (%) 80
03aa25
40
40
0 0 50 100 150 Tsp (°C) 200
0 0 50 100 150 Tsp (°C) 200
P tot P der = ------------------------ × 100 % P °
tot ( 25 C )
VGS ≥ 4.5 V
ID I der = -------------------- × 100 % I °
D ( 25 C )
Fig 1. Normalized total power dissipation as a function of solder point temperature
102 ID (A) 10 Limit RDSon = VDS / ID
Fig 2. Normalized continuous drain current as a function of solder point temperature
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tp = 10 µ s 1 ms 10 ms
1
DC
100 ms 1s
10-1
10-2 10-1
1
10 VDS (V)
102
Tsp = 25 °C; IDM is single pulse
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14724
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 24 March 2005
3 of 12
Philips Semiconductors
PMWD16UN
www.DataSheet4U.com
Dual N-channel µTrenchMOS™ ultra low level FET
5. Thermal characteristics
Table 4: Rth(j-sp) Rth(j-a) Thermal characteristics Conditions Figure 4 mounted on a printed-circuit board; minimum footprint; vertical in still air Min Typ 100 Max 40 Unit K/W K/W thermal resistance from junction to solder point thermal resistance from junction to ambient Symbol Parameter
102 Zth(j-sp) (K/W)
003aaa267
δ = 0.5 0.2 0.1 0.05 0.02
δ= tp T
10
1 single pulse
P
tp
t T
10-1 10-4
10-3
10-2
10-1
1
10
tp (s)
102
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration
9397 750 14724
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 24 March 2005
4 of 12
Philips Semiconductors
PMWD16UN
www.DataSheet4U.com
Dual N-channel µTrenchMOS™ ultra low level FET
6. Characteristics
Table 5: Characteristics Tj = 25 °C unless otherwise specified. Symbol V(BR)DSS Parameter drain-source breakdown voltage Conditions ID = 250 µA; VGS = 0 V Tj = 25 °C Tj = −55 °C VGS(th) IDSS gate-source threshold voltage drain-source leakage current ID = 1 mA; VDS = VGS; Figure 9 and 10 VDS = 20 V; VGS = 0 V Tj = 25 °C Tj = 150 °C IGSS RDSon gate-source leakage current drain-source on-state resistance VGS = ±10 V; VDS = 0 V VGS = 4.5 V; ID = 3.5 A; Figure 7 and 8 Tj = 25 °C Tj = 150 °C VGS = 1.8 V; ID = 3.5 A; Figure 7 and 8 VGS = 2.5 V; ID = 3.5 A; Figure 7 and 8 Dynamic characteristics Qg(tot) Qgs Qgd Ciss Coss Crss td(on) tr td(off) tf VSD trr Qr total gate charge gate-source charge gate-drain (Miller) charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain (diode forward) voltage IS = 4 A; VGS = 0 V; Figure 12 reverse recovery time recovered charge IS = 4 A; dIS/dt = −100 A/µs; VGS = 0 V; VR = 20 V VDS = 10 V; RL = 10 Ω; VGS = 4.5 V; RG = 6 Ω VGS = 0 V; VDS = 16 V; f = 1 MHz; Figure 11.