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74AUP1G373 Dataheets PDF



Part Number 74AUP1G373
Manufacturers NXP Semiconductors
Logo NXP Semiconductors
Description Low-power D-type transparent latch
Datasheet 74AUP1G373 Datasheet74AUP1G373 Datasheet (PDF)

74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 03 — 9 January 2008 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the l.

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74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 03 — 9 January 2008 www.DataSheet4U.com Product data sheet 1. General description The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q output follows the data (D) input. When pin LE is LOW, the latch stores the information that was present at the D-input one set-up time preceding the HIGH-to-LOW transition of pin LE. When pin OE is LOW, the contents of the latch is available at the (Q) output. When pin OE is HIGH, the output goes to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latch. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114E Class 3A exceeds 5000 V x MM JESD22-A115-A exceeds 200 V x CDM JESD22-C101-C exceeds 1000 V s Low static power consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA per JESD 78 Class II s Inputs accept voltages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF circuitry provides partial Power-down mode operation s Multiple package options s Specified from −40 °C to +85 °C and −40 °C to +125 °C NXP Semiconductors 74AUP1G373 w w w . D a t a Low-power D-type transparent latch; 3-state 3. Ordering information Table 1. Ordering information Package Temperature range Name 74AUP1G373GW 74AUP1G373GM 74AUP1G373GF −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C SC-88 XSON6 XSON6 Description plastic surface-mounted package; 6 leads Version SOT363 Type number plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Marking code aW aW aW Type number 74AUP1G373GW 74AUP1G373GM 74AUP1G373GF 5. Functional diagram D D Q Q 3 D Q 4 1 C1 4 EN 001aae248 LE LE 1 LE OE 001aae247 3 6 LE 6 OE 001aae249 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G373_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 January 2008 2 of 22 NXP Semiconductors 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 6. Pinning information 6.1 Pinning 74AUP1G373 74AUP1G373 LE GND 1 2 6 5 OE GND VCC D D 3 001aae250 LE 1 6 OE LE GND 74AUP1G373 1 2 3 6 5 4 OE VCC Q 2 5 VCC 3 4 Q D 4 Q 001aae251 001aae252 Transparent top view Transparent top view Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Symbol LE GND D Q VCC OE Pin description Pin 1 2 3 4 5 6 Description latch enable input (active HIGH) ground (0 V) data input latch output supply voltage output enable input (active LOW) 7. Functional description Table 4. Function table[1] Input OE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs [1] Operating modes Internal latch LE H H L L X D L H l h X L H L H X Output Q L H L H Z L L L L H H = HIGH voltage level; h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition; X = Don’t care; Z = high-impedance OFF-state. 74AUP1G373_3 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 — 9 January 2008 3 of 22 NXP Semiconductors 74AUP1G373 www.DataSheet4U.com Low-power D-type transparent latch; 3-state 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK VI IOK VO IO ICC IGND Tstg Ptot [1] [2] Parameter supply voltage input clamping current input voltage output clamping current output voltage output current supply current ground current storage temperature total power dissipation Conditions VI < 0 V [1] Min −0.5 −50 −0.5 [1] Max +4.6 +4.6 ±50 +4.6 ±20 50 +150 250 Unit V mA V mA V mA mA mA °C mW VO > VCC or VO < 0 V Active mode and Power-down mode VO = 0 V to VCC −0.5 −50 −65 Tamb = −40 °C to +125 °C [2] - The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For .


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