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HYS64T256022EDL-3S-B

Qimonda AG

200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules

November 2006 www.DataSheet4U.com HYS64T256022EDL–[25F/2.5]–B HYS64T256022EDL–[3/3S]–B HYS64T256022EDL–3.7–B 200-Pin Du...


Qimonda AG

HYS64T256022EDL-3S-B

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November 2006 www.DataSheet4U.com HYS64T256022EDL–[25F/2.5]–B HYS64T256022EDL–[3/3S]–B HYS64T256022EDL–3.7–B 200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules DDR2 SDRAM SO-DIMM SDRAM RoHS Compliant Internet Data Sheet Rev. 1.0 Internet Data Sheet www.DataSheet4U.com HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules HYS64T256022EDL–[25F/2.5]–B; HYS64T256022EDL–[3/3S]–B; HYS64T256022EDL–3.7–B Revision History: 2006-11, Rev. 1.0 Page All All Subjects (major changes since last revision) Adapted internet edition Initial Document We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-01 11172006-DXYK-2PPW 2 Internet Data Sheet www.DataSheet4U.com HYS64T256022EDL–[25F/2.5/3/3S/3.7]–B Small Outline DDR2 SDRAM Modules 1 Overview This chapter gives an overview of the 200-Pin Dual Die Small-Outline-DDR2-SDRAM Modules product family and describes its main characteristics. 1.1 Features Programmable self refresh rate via EMRS2 setting Programmable partial array refresh via EMRS2 settings Average Refresh Period 7.8 µs at a TCASE lower than 85°C, 3.9µs between 85°C and 95°C. DCC enabling via EMRS2 setting All inputs and outputs SSTL_18 compatible Off-Chip Driver Impedance Adjust...




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