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HYB18H1G321AF-11 Dataheets PDF



Part Number HYB18H1G321AF-11
Manufacturers Qimonda AG
Logo Qimonda AG
Description GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM
Datasheet HYB18H1G321AF-11 DatasheetHYB18H1G321AF-11 Datasheet (PDF)

October 2007 www.DataSheet4U.com HYB18H1G321AF–10/11/14 GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM RoHS compliant Internet Data Sheet Rev. 0.92 Internet Data Sheet www.DataSheet4U.com HYB18H1G321AF–10/11/14 1-Gbit GDDR3 HYB18H1G321AF–10/11/14 Revision History: 2007-10, Rev. 0.92 Page All 39 36 All All Subjects (major changes since last revision) tWR changed from 14 to 13 tRP at Speed Bin -10 is changed from 13 to 14 IDD Values were added. Typo changes. Adapted internet editition Previo.

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October 2007 www.DataSheet4U.com HYB18H1G321AF–10/11/14 GDDR3 Graphics RAM 1-Gbit GDDR3 Graphics RAM RoHS compliant Internet Data Sheet Rev. 0.92 Internet Data Sheet www.DataSheet4U.com HYB18H1G321AF–10/11/14 1-Gbit GDDR3 HYB18H1G321AF–10/11/14 Revision History: 2007-10, Rev. 0.92 Page All 39 36 All All Subjects (major changes since last revision) tWR changed from 14 to 13 tRP at Speed Bin -10 is changed from 13 to 14 IDD Values were added. Typo changes. Adapted internet editition Previous Revision: Rev. 0.91, 2007-08-08 Previous Revision: Rev. 0.80, 2007-07-10 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev411 / 3.31 QAG / 2007-01-22 06122007-MW7D-3G3M 2 Internet Data Sheet www.DataSheet4U.com HYB18H1G321AF–10/11/14 1-Gbit GDDR3 1 1.1 Overview Features • tWR programmable for Writes with Auto-Precharge • Data mask for write commands • Single ended READ strobe (RDQS) per byte. RDQS edgealigned with READ data • Single ended WRITE strobe (WDQS) per byte. WDQS center-aligned with WRITE data • DLL aligns RDQS and DQ transitions with Clock • Programmable IO interface including on chip termination (ODT) • Autoprecharge option with concurrent auto precharge support • 8k Refresh (32ms) • Autorefresh and Self Refresh • PG-TFBGA-136 package • Calibrated output drive. Active termination support • RoHS Compliant Product 1) This chapter lists all main features of the product family HYB18H1G321AF–10/11/14 and the ordering information. • 1.8 V VDDQ IO voltage • 1.8 V VDD core voltage • Monolithic 1Gbit GDDR3 with an internally programmable organization of either two separate 512MBit memories (2048 K x 32 I/O x 8 banks) with separate Chip Select, or one 1Gb memory (4096 K x 32 I/O x 8 banks) • Two CS: 4096 rows and 512 columns (128 burst start locations) per bank – One CS: 8192 rows and 512 columns (128 burst start locations) per bank • Differential clock inputs (CLK and CLK) • CAS latencies of 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 • Write latencies of 3, 4, 5, 6, 7 • Burst sequence with length of 4, 8 • 4n pre fetch • Short RAS to CAS timing for Writes • tRAS Lockout support TABLE 1 Ordering Information Part Number1) HYB18H1G321AF–10/11/14 Organization ×32 Clock (MHz) 1000 @CL12 700 @CL11 900 @CL11 1) HYB: designator for memory components 18H: VDDQ = 1.8V 1G: 1 Gbit 32: x32 organization A: Product Revision F: Lead and Halogen-Free Package PG-TFBGA-136 1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers. Rev. 0.92, 2007-10 06122007-MW7D-3G3M 3 Internet Data Sheet www.DataSheet4U.com HYB18H1G321AF–10/11/14 1-Gbit GDDR3 1.2 Description The Qimonda 1-Gbit GDDR3 Graphics RAM is a high speed memory device, designed for high bandwidth intensive applications like PC graphics systems. The chip is programmable into two different configurations. In the default mode the architecture is organized as two 512 Mbit memories of 8 banks, each (two CS mode). In an alternate configuration, it behaves as a conventional, 8-bank 1 Gbit DRAM (one CS mode). Note that at 1000 MHz speed grade only one CS mode is supported. HYB18H1G321AF–10/11/14 uses a double data rate interface and a 4n-pre fetch architecture. The GDDR3 interface transfers two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n-pre fetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, onehalf-clock-cycle data transfers at the I/O pins. Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are centeraligned with data for write commands. The HYB18H1G321AF–10/11/14 operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to both edges of RDQS. In this document references to “the positive edge of CLK” imply the crossing of the positive edge of CLK and the negative edge of CLK. Similarly, the “negative edge of CLK” refers to the crossing of the negative edge of CLK and the positive edge of CLK. References to R.


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