GS8662S18E-333

Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features Simultaneous Read and Write SigmaSIO™ Interface JEDEC-standard pinout and package Dual Double Data Rate interface Byte Write controls sampled at data-in time DLL circuitry for wide output data valid window and future frequency scaling Burst of 2 Read and Write 1.8 V +100/–100 mV core power supply 1.5 V or 1.8 V HSTL Interface Pipelined read operation Fully coherent read and write pipelines ZQ mode pin for programmable output drive strength IEEE 1149.1 JTAG-compliant Boundary Scan Pin-compatible with future 144Mb devices 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package RoHS-compliant 165-bump BGA package available 72Mb Burst of 2 DDR SigmaSIO-II SRAM 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 SigmaRAM™ Family Overview GS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also all...