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GS8662S18E-300 Dataheets PDF



Part Number GS8662S18E-300
Manufacturers GSI Technology
Logo GSI Technology
Description DDR SigmaSIO-II SRAM
Datasheet GS8662S18E-300 DatasheetGS8662S18E-300 Datasheet (PDF)

Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • F.

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Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface • Byte Write controls sampled at data-in time • DLL circuitry for wide output data valid window and future frequency scaling • Burst of 2 Read and Write • 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with future 144Mb devices • 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package available 72Mb Burst of 2 DDR SigmaSIO-II SRAM 333 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Bottom View 165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array JEDEC Std. MO-216, Variation CAB-1 SigmaRAM™ Family Overview GS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. Clocking and Addressing Schemes A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 1M addressable index). Parameter Synopsis - 333 tKHKH tKHQV 3.0 ns 0.45 ns -300 3.3 ns 0.45 ns -250 4.0 ns 0.45 ns -200 5.0 ns 0.45 ns -167 6.0 ns 0.5 ns Rev: 1.01 9/2005 1/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 8M x 8 SigmaQuad SRAM—Top View 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 SA NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC NW0 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. NW0 controls writes to D0:D3. NW1 controls writes to D4:D7. 2. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 2/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 8M x 9 SigmaQuad SRAM—Top View 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC Doff NC NC NC NC NC NC TDO 2 SA NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 SA NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC NC TDI 11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch Notes: 1. BW controls writes to D0:D7 1. It is recommended that H1 be tied low for compatibility with future devices. Rev: 1.01 9/2005 3/37 © 2005, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Preliminary GS8662S08/09/18/36E-333/300/250/200/167 www.DataSheet4U.com 4M x 18 SigmaQuad SRAM—Top View 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF.


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