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STATIC RAM. IS61LF6436A Datasheet

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STATIC RAM. IS61LF6436A Datasheet






IS61LF6436A RAM. Datasheet pdf. Equivalent




IS61LF6436A RAM. Datasheet pdf. Equivalent





Part

IS61LF6436A

Description

SYNCHRONOUS FLOW-THROUGH STATIC RAM



Feature


IS61LF6436A IS61LF6432A 64K x 32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FE ATURES • Internal self-timed write cy cle • Individual Byte Write Control a nd Global Write • Clock controlled, r egistered address, data and control • Interleaved or linear burst sequence c ontrol using MODE input • Three chip enables for simple depth expansion and address pipelining • Common .
Manufacture

Integrated Silicon Solution

Datasheet
Download IS61LF6436A Datasheet


Integrated Silicon Solution IS61LF6436A

IS61LF6436A; data inputs and data outputs • Power-d own control by ZZ input • JEDEC 100-P in TQFP package • Power Supply: +3.3V VDD +3.3V or 2.5V VDDQ • Control pin s mode upon power-up: – MODE in inter leave burst mode – ZZ in normal opera tion mode • Industrial Temperature Av ailable: (-40oC to +85oC) • Lead-free available www.DataSheet4U.com ISSI O CTOBER 2005 ® DESCRIPTION The IS.


Integrated Silicon Solution IS61LF6436A

SI IS61LF6432A and IS61LF6436A are high- speed, low-power synchronous static RAM designed to provide a burstable, high- performance, memory. IS61LF6432A is org anized as 65,536 words by 32 bits. IS61 LF6436A is organized as 65,536 words by 36 bits. They are fabricated with ISSI 's advanced CMOS technology. The device integrates a 2-bit burst counter, high -speed SRAM core, .


Integrated Silicon Solution IS61LF6436A

and high-drive capability outputs into a single monolithic circuit. All synchro nous inputs pass through registers cont rolled by a positive-edge-triggered sin gle clock input. Write cycles are inter nally self-timed and are initiated by t he rising edge of the clock input. Writ e cycles can be from one to four bytes wide as controlled by the write control inputs. Separate .

Part

IS61LF6436A

Description

SYNCHRONOUS FLOW-THROUGH STATIC RAM



Feature


IS61LF6436A IS61LF6432A 64K x 32, 64Kx36 SYNCHRONOUS FLOW-THROUGH STATIC RAM FE ATURES • Internal self-timed write cy cle • Individual Byte Write Control a nd Global Write • Clock controlled, r egistered address, data and control • Interleaved or linear burst sequence c ontrol using MODE input • Three chip enables for simple depth expansion and address pipelining • Common .
Manufacture

Integrated Silicon Solution

Datasheet
Download IS61LF6436A Datasheet




 IS61LF6436A
IS61LF6436A
IS61LF6432A
64K x 32, 64Kx36
SYNCHRONOUS FLOW-THROUGH
STATIC RAM
ISSI®
www.DataSheet4U.com
OCTOBER 2005
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control
using MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP package
• Power Supply:
+3.3V VDD
+3.3V or 2.5V VDDQ
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
• Industrial Temperature Available:
(-40oC to +85oC)
• Lead-free available
DESCRIPTION
The ISSI IS61LF6432A and IS61LF6436A are high-speed,
low-power synchronous static RAM designed to provide a
burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with ISSI's advanced CMOS technology. The device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BWa controls DQa, BWb controls DQb, BWc controls DQc,
BWd controls DQd, conditioned by BWE being LOW. A
LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the
ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
8.5
8.5
11
90
Unit
ns
ns
MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
1




 IS61LF6436A
IS61LF6436A
IS61LF6432A
BLOCK DIAGRAM
CLK
ADV
ADSC
ADSP
A
17/18
ISSI®
www.DataSheet4U.com
MODE
CLK Q0
BINARY
COUNTER
CE Q1
CLR
A0'
A1'
DQ
ADDRESS
REGISTER
CE
CLK
A0, A1
14
64Kx32;
64Kx36
MEMORY ARRAY
16
32, 36
32, 36
GW
BWE
BW(a-d)
x32/x36: a-d
D DQ(a-d) Q
BYTE WRITE
REGISTERS
CLK
CE
CE2
CE2
OE
2
DQ
ENABLE
REGISTER
CE
CLK
4
INPUT
REGISTERS
CLK
32, 36
DQa - DQd
OE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05




 IS61LF6436A
IS61LF6436A
IS61LF6432A
PIN CONFIGURATION
100-Pin TQFP
NC
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
NC
ISSI®
www.DataSheet4U.com
64K x 32
PIN DESCRIPTIONS
A0, A1
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW Synchronous Global Write Enable
CE, CE2, CE2 Synchronous Chip Enable
OE Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE
Burst Sequence Mode Selection
VDD +3.3V Power Supply
Vss Ground
VDDQ
Isolated Output Buffer Supply: +3.3V
or 2.5V
ZZ Snooze Enable
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B
08/25/05
3






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