Document
HT48E70
I/O Type 8-Bit MTP MCU With EEPROM
Features
· Operating voltage: · HALT function and wake-up feature reduce power
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fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function · 56 bidirectional I/O lines (max.) · 1 interrupt input shared with an I/O line · 2´16-bit programmable timer/event counter with over-
consumption
· 16-level subroutine nesting · Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction · 16-bit table read instruction · 63 powerful instructions · 106 erase/write cycles EEPROM data memory · EEPROM data retention > 10 years · All instructions in one or two machine cycles · In system programming (ISP) · 48-pin SSOP, 64-pin QFP package
flow interrupt
· On-chip crystal and RC oscillator · Watchdog Timer · 1,000 erase/write cycles MTP program memory · 8192´16 program memory ROM (MTP) · 256´8 data memory EEPROM · 224´8 data memory RAM
General Description
The HT48E70 is an 8-bit high performance, RISC architecture microcontroller device specifically designed for multiple I/O control product applications. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc.
Rev. 1.00
1
September 16, 2005
HT48E70
Block Diagram
T M R 1 C M U X T M R 1 L T M R 1 H In te rru p t C ir c u it S T A C K P ro g ra m M e m o ry P ro g ra m C o u n te r IN T C fS /4 T M R 1
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IN T
Y S
T M R 0 L T M R 0 H T M R 0 C
M U
fS X
Y S
/4
T M R 0
E N /D IS In s tr u c tio n R e g is te r M P M U X W D T S D A T A M e m o ry W D T P r e s c a le r W D T M U X W D T O S C P A 0 ~ P A 7 fS
Y S
/4
P A C In s tr u c tio n D e c o d e r A L U T im in g G e n e ra to r S h ifte r M U X P A P B C S T A T U S P B P C C P C P D C P D P E C P E P F C P F D a ta M e m o ry E E P R O M E E C R P G C P G
P O R T A
P O R T B
P B 0 /B Z P B 1 /B Z P B 2 ~ P B 7
P O R T C
P C 0 ~ P C 7
O S C 2
O S R V V
C 1 E S D D S S
A C C
P O R T D
P D 0 ~ P D 7
B P
P O R T E
P E 0 ~ P E 7
P O R T F
P F 0 ~ P F 7
P O R T G
P G 0 ~ P G 7
Rev. 1.00
2
September 16, 2005
HT48E70
Pin Assignment
P B 5 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 P B 4 P A 3 P A 2 P A 1 P A 0 P B 3 P B 2 P B 1 /B Z P B 0 /B Z P E 3 P E 2 P E 1 P E 0 P D 7 P D 6 P D 5 P D 4 V S S IN T T M R 0 P C 0 P C 1 P C 2 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 P B 6 P B 7 P A 4 P A 5 P A 6 P A 7 P F 0 P F 1 P F 2 P F 3 O S C 2 O S C 1 V D D R E S T M R 1 P D 3 P D 2 P D 1 P D 0 P C 7 P C 6 P C 5 P C 4 P C 3 P A 1 P A 0 P E 7 P E 6 P E 5 P E 4 P B 3 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 IN T T M R 0 P G 0 P G 1 P G 2 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 P G 3 P C 0 P C 1 P C 2 P C 3 P C 4 P C 5 P B 2 P B 1 /B Z P B 0 /B Z P E 3 P E 2 P E 1 P E 0 P D 7 P D 6 P D 5 P D 4 V S S 6 5 4 3 2 1 P G 6 P G 7 P G 4 P G 5 P A 2 P A 3 P B 4 P B 5 P B 6 P B 7 P A 4 P A 5 P A 6
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6 4 6 3 6 2 6 1 6 0
5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2
5 1 5 0 4 9 4 8 4 7 4 6 4 5 4 4
P A 7 P F 0 P F 1 P F 2 P F 3 O S C 2 O S C 1 P F 4 P F 5 P F 6 P F 7 V D D R E S T M R 1 P D 3 P D 2 P D 1 P D 0 P C 7
H T 4 8 E 7 0 6 4 Q F P -A
4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 3
P C 6
H T 4 8 E 7 0 4 8 S S O P -A
Pad Assignment
P A P A P A P B P B P B P B P G P G P G P G P A P A 2 P A 1
1 P A P E P E P E P E P B P B P B 1 /B P B 0 /B P E P E P E P E P D P D P D P D Z 2 0 6 4 5 7 1 3 0 2 4 5 5 4 2 Z 3 8 7 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 6 3 6 7 6 7 (0 ,0 ) 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 P F P F P F P F V D 7 D 4 5 6 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2
4
5
6
3
6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1 5 0 4 9 4 8 3 O S C 2 O S C 1 P A P F P F P F P F 0 1 2 7 R E S T M R 1 P D 3 P D 2 3 3 3 4 3 5 3 6 3 7 3 8
4 T R IM 2 T R IM 3 P D 1 P D 0 P C 7 T R IM 1
5
6
7
4
5
6
7
P C P C P C P C P C P C P C P G P G P G P G T M IN T V S S 6 5 4 3 2 1 0 3 2 1 R 0 0
* The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 3 September 16, 2005
HT48E70
Pad Description
Pad Name I/O Options Wake-up Pull-high* CMOS or Schmitt Input Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by options. Software instructions determine if the pin is a CMOS output or Schmitt trigger input or CMOS input with or without pull-high resistor (by options). Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt trigger input with pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with BZ and BZ respectiv.