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Mbit PSRAM. M36L0T7050B2 Datasheet

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Mbit PSRAM. M36L0T7050B2 Datasheet






M36L0T7050B2 PSRAM. Datasheet pdf. Equivalent




M36L0T7050B2 PSRAM. Datasheet pdf. Equivalent





Part

M36L0T7050B2

Description

(M36L0T7050T2 / M36L0T7050B2) 128 Mbit Flash memory and 32 Mbit PSRAM



Feature


www.DataSheet4U.com M36L0T7050T2 M36L0T 7050B2 128 Mbit (Multiple Bank, Multi-L evel, Burst) Flash memory and 32 Mbit ( 2Mb x16) PSRAM, Multi-Chip Package Prel iminary Data Feature summary ■ Mult i-Chip Package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multi-level, Bur st) Flash Memory – 1 die of 32 Mbit ( 2Mb x16) Pseudo SRAM Supply voltage – VDDF = 1.7 to 1.95V – VCC.
Manufacture

Numonyx

Datasheet
Download M36L0T7050B2 Datasheet


Numonyx M36L0T7050B2

M36L0T7050B2; P = VDDQ = 2.7 to 3.1V – VPPF = 9V for fast program Electronic signature – Manufacturer Code: 20h – Device Code (Top Flash Configuration) M36L0T7050T2: 88C4h – Device Code (Bottom Flash Co nfiguration) M36L0T7050B2: 88C5h ECOPAC K® packages available ■ ■ FBGA TFBGA88 (ZAQ) 8 x 10mm ■ ■ B lock locking – All blocks locked at p ower-up – Any combination of blocks can.


Numonyx M36L0T7050B2

be locked with zero latency – WP for Block Lock-Down – Absolute Write Prot ection with VPP = VSS Security – 64 b it unique device number – 2112 bit us er programmable OTP Cells Common Flash Interface (CFI) 100,000 program/erase c ycles per block Flash memory ■ Sync hronous / Asynchronous Read – Synchro nous Burst Read mode: 52MHz – Random Access: 85ns Synchronous Burst R.


Numonyx M36L0T7050B2

ead Suspend Programming time – 2.5µs typical Word program time using Buffer Enhanced Factory Program command Memory organization – Multiple Bank Memory Array: 8 Mbit Banks – Parameter Block s (Top or Bottom location) Dual operati ons – program/erase in one Bank while read in others – No delay between re ad and write operations ■ ■ ■ PSRAM ■ ■ ■ ■ ■ ■ Access time: 6.

Part

M36L0T7050B2

Description

(M36L0T7050T2 / M36L0T7050B2) 128 Mbit Flash memory and 32 Mbit PSRAM



Feature


www.DataSheet4U.com M36L0T7050T2 M36L0T 7050B2 128 Mbit (Multiple Bank, Multi-L evel, Burst) Flash memory and 32 Mbit ( 2Mb x16) PSRAM, Multi-Chip Package Prel iminary Data Feature summary ■ Mult i-Chip Package – 1 die of 128 Mbit (8 Mb x16, Multiple Bank, Multi-level, Bur st) Flash Memory – 1 die of 32 Mbit ( 2Mb x16) Pseudo SRAM Supply voltage – VDDF = 1.7 to 1.95V – VCC.
Manufacture

Numonyx

Datasheet
Download M36L0T7050B2 Datasheet




 M36L0T7050B2
www.DataSheet4U.com
M36L0T7050T2
M36L0T7050B2
128 Mbit (Multiple Bank, Multi-Level, Burst) Flash memory
and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package
Preliminary Data
Feature summary
Multi-Chip Package
– 1 die of 128 Mbit (8Mb x16, Multiple Bank,
Multi-level, Burst) Flash Memory
– 1 die of 32 Mbit (2Mb x16) Pseudo SRAM
Supply voltage
– VDDF = 1.7 to 1.95V
– VCCP = VDDQ = 2.7 to 3.1V
– VPPF = 9V for fast program
Electronic signature
– Manufacturer Code: 20h
– Device Code (Top Flash Configuration)
M36L0T7050T2: 88C4h
– Device Code (Bottom Flash Configuration)
M36L0T7050B2: 88C5h
ECOPACK® packages available
Flash memory
Synchronous / Asynchronous Read
– Synchronous Burst Read mode: 52MHz
– Random Access: 85ns
Synchronous Burst Read Suspend
Programming time
– 2.5µs typical Word program time using
Buffer Enhanced Factory Program
command
Memory organization
– Multiple Bank Memory Array: 8 Mbit Banks
– Parameter Blocks (Top or Bottom location)
Dual operations
– program/erase in one Bank while read in
others
– No delay between read and write
operations
FBGA
TFBGA88 (ZAQ)
8 x 10mm
Block locking
– All blocks locked at power-up
– Any combination of blocks can be locked
with zero latency
– WP for Block Lock-Down
– Absolute Write Protection with VPP = VSS
Security
– 64 bit unique device number
– 2112 bit user programmable OTP Cells
Common Flash Interface (CFI)
100,000 program/erase cycles per block
PSRAM
Access time: 65ns
8-Word Page Access capability: 18ns
Low standby current: 100µA
Deep power down current: 10µA
Compatible with standard LPSRAM
Power-down modes
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
November 2007
Rev 0.2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/22
www.numonyx.com
1




 M36L0T7050B2
Contents
Contents
M36L0T7050T2w,wMw3.D6aLta0STh7e0e5t40UB.c2om
1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Address Inputs (A0-A22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Data Input/Output (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Flash Chip Enable (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Flash Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Flash Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Flash Write Protect (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.7 Flash Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.8 Flash Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.9 Flash Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.10 Flash Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.11 PSRAM Chip Enable Input (E1P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.12 PSRAM Chip Enable Input (E2P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.13 PSRAM Write Enable (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.14 PSRAM Output Enable (GP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.15 PSRAM Upper Byte Enable (UBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.16 PSRAM Lower Byte Enable (LBP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.17 VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.18 VCCP Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.19 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.20 VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.21 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22




 M36L0T7050B2
M36L0T7050T2, M36L0T7050B2
www.DataCShoenette4nU.tcsom
7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22






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