ICSLV810

ICSLV810 www.DataSheet4U.com Buffer/Clock Driver Description The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer. This device is specifically designed for data communications clock management. The large fanout from a single input line reduces loading on the input clock. The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution. Features Packaged in 20-pin QSOP/SSOP Split 1:10 fanout Buffer Maximum skew between outputs of different packages 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40° C to +85° C 3.3 V tolerant input when VDDA=2.5 V Available in Pb (lead) free packaging Block Diagram VDDA CLK 1 CLK 2 CLK 3 CLK 4 CLKIN CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK 10 VDDB VDDC MDS LV810 F Integrated Circuit Systems, Inc. ● 1 525 Race Street, San Jose, CA 95126 ● Revision 101305 tel (408) 297-1201 ● www.icst.com ICSLV810 Buffer/Clock Driver www.DataSheet4U.com Pin Assignment CLKIN GND CLK 1 VDDA CLK 2 GND CLK 3 VDDA CLK 4 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDB CLK 10 CLK 9 GND CLK 8 VDDC CLK 7 GND CLK 6 CLK 5 20 pin (150mil) SSOP Pin Descriptions Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name CLKIN GND CLK1 VDDA CLK2 GND CLK3 VDDA CLK4 GND CLK5 CLK6 GND CLK7 VDDC CLK8 GND CLK9 CLK10 VDDB Pin ...