ICS85408

Integrated Circuit Systems, Inc. ICS85408 LOW SKEW, 1-TO-8 DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP FEATURES 8 Differential LVDS outputs CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Maximum output frequency: 700MHz Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks Translates any single-ended input signal to LVDS with resistor bias on nCLK input Multiple output enable inputs for disabling unused outputs in reduced fanout applications Output skew: 50ps (maximum) Part-to-part skew: 550ps (maximum) Propagation delay: 2.4ns (maximum) 3.3V operating supply 0°C to 70°C ambient operating temperature Lead-Free package RoHS compliant GENERAL DESCRIPTION The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution HiPerClockS™ Chip and a member of the HiPerClock S ™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS clock signals. ICS www.DataSheet4U.com Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM OE Q0 nQ0 Q1 ...