ICS85411

Integrated Circuit Systems, Inc. ICS85411 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER FEATURES 2 differential LVDS outputs 1 differential CLK, nCLK clock input CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL Maximum output frequency: 650MHz Translates any single ended input signal to LVDS levels with resistor bias on nCLK input Output skew: 20ps (maximum) Part-to-part skew: 250ps (maximum) Additive phase jitter, RMS: 0.05ps (typical) Propagation delay: 2.5 ns (maximum) 3.3V operating supply 0°C to 70°C ambient operating temperature Lead-Free package available Industrial temperature information available upon request GENERAL DESCRIPTION The ICS85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85411 ideal for those clock distribution applications demanding well defined performance and repeatability. ICS www.DataSheet4U.com BLOCK DIAGRAM CLK nCLK Q0 nQ0 Q1 nQ1 PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND ICS85411 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 85411AM www.icst.com/products/hiperclocks.html 1 REV. B JUN...