ICS854S013

PRELIMINARY LOW SKEW, DUAL, 1-TO-3 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ICS854S013 General Description The ICS854S013 is a low skew, high performance Dual 1-to-3 Differential-to-LVDS Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. The ICS854S013 is characterized to operate from a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S013 ideal for those clock distribution applications demanding well defined performance and repeatability. www.DataSheet4U.com Features Two differential LVDS output banks Two differential clock input pairs PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Maximum output frequency: >3GHz Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input Output skew: <25ps (typical) Bank skew: <50ps (typical) Propagation delay: TBD Additive phase jitter, RMS: 0.15ps (typical) Full 3.3V power supply 0°C to 70°C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS Block Diagram QA0 nQA0 PCLKA Pulldown nPCLKA Pullup QA1 nQA1 QA2 nQA2 QB0 nQB0 PCLKB Pulldown nPCLKB Pullup QB1 nQB1 QB2 nQB2 Pin Assignment nQA0 QA0 VDD PCLKA nPCLKA PCLKB nPCLKB VDD nQB0 QB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VDD QB2 nQB2 QB1 nQ...