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MT3270B Dataheets PDF



Part Number MT3270B
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description Wide Dynamic Range DTMF Receiver
Datasheet MT3270B DatasheetMT3270B Datasheet (PDF)

www.DataSheet.co.kr MT3170B/71B, MT3270B/71B, MT3370B/71B Wide Dynamic Range DTMF Receiver Data Sheet Features • • • • • • • • • Wide dynamic range (50 dB) DTMF Receiver Call progress (CP) detection via cadence indication 4-bit synchronous serial data output Software controlled guard time for MT3x70B Internal guard time circuitry for MT3x71B Powerdown option (MT317xB & MT337xB) 4.194304 MHz crystal or ceramic resonator (MT337xB and MT327xB) External clock input (MT317xB) Guarantees non-detectio.

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www.DataSheet.co.kr MT3170B/71B, MT3270B/71B, MT3370B/71B Wide Dynamic Range DTMF Receiver Data Sheet Features • • • • • • • • • Wide dynamic range (50 dB) DTMF Receiver Call progress (CP) detection via cadence indication 4-bit synchronous serial data output Software controlled guard time for MT3x70B Internal guard time circuitry for MT3x71B Powerdown option (MT317xB & MT337xB) 4.194304 MHz crystal or ceramic resonator (MT337xB and MT327xB) External clock input (MT317xB) Guarantees non-detection of spurious tones Ordering Information MT3170/71BE MT3270/71BE MT3370/71BS MT3370/71BN MT3370/71BSR MT3371BNR MT3270/71BE1 MT3171BE1 MT3170BE1 MT3370/BN1 MT3370/71BS1 MT3370/71BSR1 8 Pin PDIP 8 Pin PDIP 18 Pin SOIC 20 Pin SSOP 18 Pin SOIC 20 Pin SSOP 8 Pin PDIP* 8 Pin PDIP* 8 Pin PDIP** 20 Pin SSOP* 18 Pin SOIC* 18 Pin SOIC* *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40°C to 85°C Tubes Tubes Tubes Tubes Tape & Reel Tape & Reel Tubes Tubes Tubes Tubes Tubes Tape & Reel August 2005 Applications • • • Integrated telephone answering machine End-to-end signalling Fax Machines PWDN VDD VSS ➀ Voltage Bias Circuit Steering Circuit High Group Filter Antialias Filter Dial Tone Filter Low Group Filter Digital Detector Algorithm Code Converter and Latch Digital Guard Time➂ Parallel to Serial Converter & Latch ESt or DStD ACK INPUT AGC Mux SD OSC2 OSC1 (CLK) ➁ Oscillator and Clock Circuit To All Chip Clocks Energy Detection ➀ MT3170B/71B and MT337xB only. ➁ MT3270B/71B and MT337xB only. ➂ MT3x71B only. Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 1995-2005, Zarlink Semiconductor Inc. All Rights Reserved. Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr MT3170B/71B, MT3270B/71B, MT3370B/71B Description Data Sheet The MT3x7xB is a family of high performance DTMF receivers which decode all 16 tone pairs into a 4-bit binary code. These devices incorporate an AGC for wide dynamic range and are suitable for end-to-end signalling. The MT3x70B provides an early steering (ESt) logic output to indicate the detection of a DTMF signal and requires external software guard time to validate the DTMF digit. The MT3x71B, with preset internal guard times, uses a delay steering (DStD) logic output to indicate the detection of a valid DTMF digit. The 4-bit DTMF binary digit can be clocked out synchronously at the serial data (SD) output. The SD pin is multiplexed with call progress detector output. In the presence of supervisory tones, the call progress detector circuit indicates the cadence (i.e., envelope) of the tone burst. The cadence information can then be processed by an external microcontroller to identify specific call progress signals. The MT327xB and MT337xB can be used with a crystal or a ceramic resonator without additional components. A power-down option is provided for the MT317xB and MT337xB. MT3170B/71B INPUT PWDN CLK VSS 1 2 3 4 8 7 6 5 VDD INPUT ESt/ DStD OSC2 ACK SD OSC1 VSS MT3270B/71B 1 2 3 4 8 7 6 5 VDD ESt/ DStD ACK SD NC INPUT PWDN OSC2 NC OSC1 NC NC VSS MT3370B/71B 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD NC NC ESt/DStD NC ACK NC SD NC NC NC INPUT PWDN NC OSC2 OSC1 VSS NC NC MT3370B/71B 1 2 3 4 5 6 7 8 9 10 20 PIN SSOP 20 19 18 17 16 15 14 13 12 11 NC NC VDD NC ESt/DStD NC ACK SD NC NC 8 PIN PLASTIC DIP 18 PIN PLASTIC SOIC Figure 2 - Pin Connections Pin Description Pin # 337xB 2 4 6 327xB 1 2 3 317xB 1 3 Name INPUT OSC2 OSC1 (CLK) Description DTMF/CP Input. Input signal must be AC coupled via capacitor. Oscillator Output. Oscillator/Clock Input. This pin can either be driven by: 1) an external digital clock with defined input logic levels. OSC2 should be left open. 2) connecting a crystal or ceramic resonator between OSC1 and OSC2 pins. Ground. (0V) Serial Data/Call Progress Output. This pin serves the dual function of being the serial data output when clock pulses are applied after validation of DTMF signal, and also indicates the cadence of call progress input. As DTMF signal lies in the same frequency band as call progress signal, this pin may toggle for DTMF input. The SD pin is at logic low in powerdown state. Acknowledge Pulse Input. After ESt or DStD is high, applying a sequence of four pulses on this pin will then shift out four bits on the SD pin, representing the decoded DTMF digit. The rising edge of the first clock is used to latch the 4-bit data prior to shifting. This pin is pulled down internally. The idle state of the ACK signal should be low. 9 11 4 5 4 5 VSS SD 13 6 6 ACK 2 Zarlink Semiconductor Inc. Datasheet pdf - http://www.DataSheet4U.net/ www.DataSheet.co.kr MT3170B/71B, MT3270B/71B, MT3370B/71B Pin Description Pin # 337xB 15 327xB 7 317xB 7 Name ESt (MT3x70B) Data Sheet Description Early Steering Output. A logic high on ESt indicates that a DTMF signal is present. ESt is at logic low in powerdown state. Delaye.


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