IS42S83200B

IS42S83200B IS42S16160B 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM ISSI ® PRELIMINARY INFORMATION MAY 2006 FEATURES Clock frequency: 166, 143 MHz Fully synchronous; all signals referenced to a positive clock edge www.DataSheet4U.com Internal bank OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. for hiding row access/precharge VDDQ VDD 3.3V 3.3V 3.3V 3.3V Power supply IS42S83200B 54-pin TSOPII IS42S16160B 54-pin TSOPII 54-ball BGA IS42S83200B IS42S16160B LVTTL interface 8M x 8 x 4 Banks 4M x16x4 Banks Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Auto Refresh (CBR) Self Refresh 8K refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Available in Industrial Temperature Available in 54-pin TSOP-II and 54-ball BGA (x16 only) Available in Lead-free KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -6 6 8 166 125 5.4 6.5 -7 7 10 143 100 5.4 6.5 Unit ns ns Mhz Mhz ns ns Copyright © 2006 Integrated Silicon Solutio...