TV00570002CDGB

TV00570002/003CDGB TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS TENTATIVE Pseudo SRAM and NOR Flash Memory Mixed Multi-Chip Package DESCRIPTION The TV00570002/003CDGB is a mixed multi-chip package containing a 33,554,432-bit pseudo static RAM and a 134,217,728-bit Nor Flash Memory. The TV00570002/003CDGB is available in a 81-pin BGA package making it suitable for a variety of applications. MCP Features Power supply voltage of 2.7 to 3.3 V Operating temperature of −30° to 85°C Package P-TFBGA81-0710-0.80BZ (Weight: 0.15 g) Nor Flash Memory Features Organization: 8M × 16 bits Power dissipation Read operating : 55 mA maximum Address Increment Read operation: 24mA maximum Page Read operating : 5 mA maximum Program / Erase operating: 15 mA maximum Standby : 10 μA maximum Access time : Random : 70 ns @CL=30pF Page : 25 ns @CL=30pF Functions Simultaneous Read/Write Page read Auto-Program , Auto Page Program Auto Block Erase , Auto Chip Erase Program Suspend / Resume Erase Suspend/Resume Data polling / Toggle bit Password block protection Block Protection/Boot Block Protection Automatic Sleep, supports for hidden ROM Area Common Flash Memory Interface (CFI) Block erase architecture 8 × 8 Kbytes / 127 × 64 Kbytes Bank architecture 16 Mbits × 8 Banks Boot block architecture TV00570002CDGB : top boot block TV00570003CDGB : bottom boot block Mode control Compatible with JEDEC standard commands Erase/Program cycles 100,000 cycles typ. Pseudo SRAM Features www.Dat...