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IDT71V416S Dataheets PDF



Part Number IDT71V416S
Manufacturers Integrated Device Technology
Logo Integrated Device Technology
Description 3.3V CMOS Static RAM
Datasheet IDT71V416S DatasheetIDT71V416S Datasheet (PDF)

3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Features 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. ◆ Equal access and cycle times – Commercial and Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Bidirectional data inputs and outputs directly LVTTL-compatible ◆ Low power consumption via chip deselect www.DataSheet4U.com ◆ Upper and Lower Byte Enable Pins ◆ Single 3.3V power supply ◆ Available in 44-pin, 400 mil plastic SOJ pa.

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3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Features 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. ◆ Equal access and cycle times – Commercial and Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Bidirectional data inputs and outputs directly LVTTL-compatible ◆ Low power consumption via chip deselect www.DataSheet4U.com ◆ Upper and Lower Byte Enable Pins ◆ Single 3.3V power supply ◆ Available in 44-pin, 400 mil plastic SOJ package and a 44pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. ◆ ◆ IDT71V416S IDT71V416L Description The IDT71V416 is a 4,194,304-bit high-speed Static RAM organized as 256K x 16. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for highspeed memory needs. The IDT71V416 has an output enable pin which operates as fast as 5ns, with address access times as fast as 10ns. All bidirectional inputs and outputs of the IDT71V416 are LVTTL-compatible and operation is from a single 3.3V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a 44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x 9mm package. Functional Block Diagram OE Output Enable Buffer A0 - A17 Address Buffers Row / Column Decoders 8 CS Chip Select Buffer 8 Sense Amps and Write Drivers High Byte Output Buffer High Byte Write Buffer 8 I/O 15 8 I/O 8 4,194,304-bit Memory Array WE Write Enable Buffer 16 8 Low Byte Output Buffer Low Byte Write Buffer 8 I/O 7 8 8 I/O 0 BHE Byte Enable Buffers BLE 3624 drw 01 JANUARY 2004 1 ©2004 Integrated Device Technology, Inc. DSC-3624/09 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Pin Configurations - SOJ/TSOP 1 2 3 4 5 6 CS 7 I/O 0 8 I/O 1 9 I/O 2 10 I/O 3 11 VDD VSS 12 I/O 4 13 I/O 5 14 www.DataSheet4U.com I/O 6 15 I/O 7 16 WE 17 A5 18 A6 19 A7 20 A8 21 A9 22 A0 A1 A2 A3 A4 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A17 A16 A15 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VDD I/O 11 I/O 10 I/O 9 I/O 8 NC* A14 A13 A12 A11 A10 Pin Configurations - 48 BGA 1 A B C D E F G H BLE I/O0 I/O1 VSS VDD I/O6 I/O7 NC 2 OE BHE I/O2 I/O3 I/O4 I/O5 NC A8 3 A0 A3 A5 A 17 NC A 14 A 12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CS I/O10 I/O11 I/O12 I/O13 WE A11 6 NC I/O8 I/O9 VDD VSS I/O14 I/O15 NC 3624 tbl 11 SO44-1 SO44-2 3624 drw 02 *Pin 28 can either be a NC or connected to Vss Top View Pin Descriptions A0 - A17 CS WE OE BHE BLE I/O0 - I/O15 VDD VSS Address Inputs Chip Select Write Enable Output Enable High Byte Enable Low Byte Enable Data Input/Output 3.3V Power Ground Input Input Input Input Input Input I/O Pwr Gnd 3624 tbl 01 SOJ Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 7 8 Unit pF pF 3624 tbl 02 48 BGA Capacitance (TA = +25°C, f = 1.0MHz) Symbol CIN CI/O Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF 3624 tbl 02b NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 2 IDT71V416S, IDT71V416L, 3.3V CMOS Static RAM 4 Meg (256K x 16-Bit) Commercial and Industrial Temperature Ranges Absolute Maximum Ratings(1) Symbol VDD VIN, VOUT TBIAS TSTG PT IOUT Rating Supply Voltage Relative to VSS Terminal Voltage Relative to VSS Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Value -0.5 to +4.6 -0.5 to VDD+0.5 -55 to +125 -55 to +125 1 50 Unit V V o o Recommended Operating Temperature and Supply Voltage Grade Commercial Industrial Temperature 0OC to +70OC –40 C to +85 C O O VSS 0V 0V VDD See Below See Below 3624 tbl 05 C C W mA 3624 tbl 04 Recommended DC Operating Conditions Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 3.0 0 2.0 -0.3(2) Typ. 3.3 0 ____ NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional www.DataSheet4U.com operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Max. 3.6 0 VDD+0.3(1) 0.8 Unit V V V V 3624 tbl 06 ____ NOTES: 1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle. 2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle. Truth Table(1) CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0-I/O7 High-Z DATAOUT High-Z DATAOUT DATAIN DATAIN High-Z High-Z High-Z I.


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