Document
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[AK4220]
AK4220
7:3 Audio Switch and 6:3 Video Switch
GENERAL DESCRIPTION The AK4220 is an AV Switch with 7:3 Audio Switches and 6:3 Video Switches. Using CMOS process to offer the high performance with low power consumption. In the Audio section, on-chip differential input circuit could separate the external ground noise. The AK4220 integrates a pop noise free circuit for power on/pff. The AK4220 is offered in a space saving 64-pin LQFP package, ideal for car navigation applications. FEATURES
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1. Audio Section • Selector for 7 inputs and 3 outputs • Differential Input Circuit for Ground Noise Cannel • THD+N: -92dB (@1Vrms) • Dynamic Range: 96dB • Channel-Independent Output Off • Pop Noise Free Circuit for Power On/Off • Channel-Independent Input Detection Circuit 2. Video Section • Selector for 6 inputs and 3 outputs • Six Composite Signal Inputs • Video Driver for Composite Signal Output (+6dB) • Channel-Independent Hi-Z Output • On-Chip Sync-tip Clamp Circuit • Frequency Range: 6MHz • S/N: 74dB • Input Detection Circuit 3. Control Section • Serial µP I/F (I2C, 4-wires serial) • Five Programmable Output pins 4. Power Supply • Analog: 4.5V ~ 5.5V • Digital: 3.0V ~ 3.6V • Low Power Consumption: 186mW 5. Ta = -40 ∼ 85 °C 6. Package: 64pin LQFP
MS0627-E-00 -1-
2007/05
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[AK4220]
AV D D 40k Ω (typ) AV S S
LIN + 1
40k Ω (typ) LO U T 1 VCO M 40k Ω (typ)
GND1 40k Ω (typ) 40k Ω (typ) R IN + 1 40k Ω (typ)
MU T E T
ROUT1
In put #1
MU T E T
O utput #1
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LIN + 2 GND2 R IN + 2 (s am e circ uit) In put #2 (s am e circ uit) LIN + 3 GND3 R IN + 3 (s am e circ uit) In put #3 O utput #2 ROUT2 LO U T 2
LIN + 4 GND4 R IN + 4
(s am e circ uit) In put #4 (s am e circ uit) LO U T 3
LIN + 5 GND5 R IN + 5
(s am e circ uit) In put #5 O utput #3
ROUT3
LIN + 6 GND6 R IN + 6
(s am e circ uit) In put #6
LIN + 7 GND7 R IN + 7
(s am e circ uit) In put #7 AD ET L
R VCO M MU T E T
O s cillator B ias ADET R
Figure 1. Audio Block
MS0627-E-00 -2-
2007/05
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[AK4220]
VVDD1 VVDD2 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VFB1 +6dB Video Drivers VVSS1 VVSS2 VVSS3 VOUT1
+6dB
VOUT2
VFB2
+6dB
VOUT3
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VFB3
Sync DET
Sync-tip TEST PDN IICN SDA/CDTI SCL/CCLK INT PDN CAD1/CSN CAD0/CDTO Control Registers Clamp (A/V control) DVDD DVSS (open drain) Q0 Q1 Q2 Q3 Q4
Figure 2. Video & Control Block
MS0627-E-00 -3-
2007/05
I
[AK4220]
■ Ordering Guide
AK4220VQ AKD4220 −40 ∼ +85°C 64pin LQFP (0.5mm pitch) Evaluation board for AK4220
■ Pin Layout
GND2 48 RIN+1 47 LIN+1 46 GND1 45 ROUT3 44 LOUT3 43 ROUT2 42 LOUT2 41 ROUT1 40 LOUT1 39 AVSS 38 VCOM 37 MUTET 36 R 35 AVDD 34 VIN6 33 VIN5 32 IICN 31 VIN4 30 VVSS1 29 VIN3 28 VVDD1 27 VIN2 26 VVSS3 25 VIN1 24 VVSS2 23 VFB3 22 VOUT3 21 VVDD2 20 VFB2 19 VOUT2 18 15 VOUT1 13 DVDD TEST 17 16 VFB1 14 DVSS CAD1 CAD0 PDN SDA
49 LIN+2 50 RIN+2 51 GND3
www.DataSheet4U.com 52
LIN+3
53 RIN+3 54 GND4 55 LIN+4 56 RIN+4 57 GND5 58 LIN+5 59 RIN+5 60 GND6 61 LIN+6 62 RIN+6 63 GND7 RIN+7 64 LIN+7
AK4220
Top View
SCL
INT
Q0
Q1
10 Q2
11 Q3
MS0627-E-00 -4-
12 Q4
1
2
3
4
5
6
7
8
9
2007/05
I
[AK4220]
PIN/FUNCTION
No. 1 2 Pin Name RIN+7 PDN CAD1 CSN SCL 4 CCLK SDA 5 CDTI CAD0 6 CDTO www.DataSheet4U.com 7 INT 8 Q0 9 Q1 10 Q2 11 Q3 12 Q4 3 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 DVDD DVSS VOUT1 VFB1 TEST VOUT2 VFB2 VVDD2 VOUT3 VFB3 VVSS2 VIN1 VVSS3 VIN2 VVDD1 VIN3 VVSS1 VIN4 IICN VIN5 VIN6 AVDD I/O I I I I I I I/O I I O O O O O O O O I I O I O I I I I I I I I Function Rch Audio Positive Input 7 Power down Mode “L”: Power down, Reset “H”: Power up The AK4220 should always be reset upon power-up. Chip Address1 (IICN pin = “L”) Chip Selector (IICN pin = “H”) Control Clock Input (IICN pin = “L”) Control Clock Input (IICN pin = “H”) Control Data Input/Output (IICN pin = “L”) Control Data Input (IICN pin = “H”) Chip Address0 (IICN pin = “L”) Control Data Output (IICN pin = “H”) Interrupt Parallel Output 0 (open drain output) Parallel Output 1 (open drain output) Parallel Output 2 (open drain output) Parallel Output 3 (open drain output) Parallel Output 4 (open drain output) Digital Power Supply Normally connected to DVSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic capacitor. Digital Ground Video Output 1 Video Feedback 1 Test pin, Connected to VVSS. Video Output 2 Video Feedback 2 Video Power Supply, 5V Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic capacitor. Video Output 3 Video Feedback 3 Video Ground2, 0V Video Input 1 Video Ground3, 0V Video Input 2 Video Power Supply, 5V Normally connected to VVSS with a 0.1μF ceramic capacitor in parallel with a 10μF electrolytic cap. Video Input 3 Video Ground1, 0V Video Input 4 Control Mode Selection “L”(Connected to VVSS): IIC Bus “H” (Connected to VVDD): 4-wire Serial Video Input 5 Video Input 6 Audio Power Supply, 5V Normally connected to AVSS with a 0.1μF ceramic capacitor in parallel with a 10.