PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Description
QL3025 pASIC 3 FPGA Data Sheet
25,000 Usable PLD Gate pASIC 3 FPGA Combining High Performance and High Density
Device Highlights
High Performance & High Density
25,000 Usable PLD Gates with 204 I/Os 300 MHz 16-bit www.DataSheet4U.com
Four Low-Skew Distributed Networks
Two array clock/control networks available
Counters, 400 MHz Datapaths 0....
