MPC8535E

Freescale Semiconductor Data Sheet: Product Preview Document Number: MPC8535EEC Rev. 2, 09/2009 MPC8535E PowerQUICC™ III Integrated Processor Hardware Specifications High-performance, 32-bit e500 core, scaling up to 1.25 GHz, that implements the Power Architecture™ technology www.DataSheet4U.com – 36-bit physical addressing – Double-precision embedded floating point APU using 64-bit operands – Embedded vector and scalar single-precision floating-point APUs using 32- or 64-bit operands – Memory management unit (MMU) Integrated L1/L2 cache – L1 cache—32-Kbyte data and 32-Kbyte instruction – L2 cache—512-Kbyte (8-way set associative) DDR2/DDR3 SDRAM memory controller with full ECC support – One 64-bit/32-bit data bus – Up to 250-MHz clock (500-MHz data rate) – Supporting up to 16 Gbytes of main memory – Using ECC, detects and corrects all single-bit errors and detects all double-bit errors and all errors within a nibble – Invoke a level of system power management by asserting MCKE SDRAM signal on-the-fly to put the memory into a low-power sleep mode – Both hardware and software options to support battery-backed main memory Integrated security engine (SEC) optimized to process all the algorithms associated with IPsec, IKE, SSL/TLS, iSCSI, SRTP, IEEE Std 802.16e™, and 3GPP. – XOR engine for parity checking in RAID storage applications Enhanced Serial peripheral interfaces (eSPI) – Support boot capability from eSPI Two enhanced three-speed Ethernet controllers (eTSECs...