Document
K7P323688M K7P321888M
1Mx36 & 2Mx18 SRAM
www.DataSheet4U.com
32Mb M-die LW SRAM Specification
119BGA with Pb & Pb-Free
(RoHS compliant)
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* Samsung Electronics reserves the right to change products or specification without notice.
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Dec. 2005 Rev 1.3
K7P323688M K7P321888M
Document Title
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
1Mx36 & 2Mx18 SRAM
www.DataSheet4U.com
Revision History
Rev. No.
Rev. 0.0 Rev. 0.1
History
- Initial Document - Recommended DC operating conditions are changed Max VDIF-CLK : VDDQ+0.3 -> VDDQ+0.6 - AC Characteristics are changed TAVKH / TDVKH / TWVKH / TSVKH : 0.4 / 0.4 / 0.4 - > 0.3 / 0.3 / 0.3 TKHAX / TKHDX / TKHWX / TKHSX : 0.5 / 0.6 / 0.7 - > 0.5 / 0.5 / 0.5 TKHAX / TKHDX / TKHWX / TKHSX : 1.6 / 1.7 / 2.0 - > 1.5 / 1.6 / 2.0
Draft Date
Apr. 2002 Feb. 2003
Remark
Advance Advance
Rev. 0.2
- PACKAGE PIN CONFIGURATION are changed Numbering each SA pins. - AC Characteristics are changed TKHQV (-33) : 0.5 - > 0.6 - PIN CAPACITANCE is changed Add Clock Pin capacitance - Fill the themal Data - Remove 333MHz Bin - JTAG DC operating conditions are changed Change VIH, VIL VOH, VOL - Add Pb free. - Modify package dimensions
Feb. 2003
Advance
Rev. 0.3
Mar. 2003
Advance
Rev. 0.4
May 2003
Advance
Rev. 1.0
Sep. 2004
Final
Rev. 1.1
Oct. 2004
Final
Rev. 1.2 Rev. 1.3
Oct. 2005 Dec. 2005
Final Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or cortact Headquarters.
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Dec. 2005 Rev 1.3
K7P323688M K7P321888M
1Mx36 & 2Mx18 Synchronous Pipelined SRAM
FEATURES
• 1Mx36 or 2Mx18 Organizations. • 1.8V VDD/1.5V or 1.8V VDDQ. • HSTL Input and Output Levels. • Differential, HSTL Clock Inputs K, K. • Synchronous Read and Write Operation • Registered Input and Registered Output • Internal Pipeline Latches to Support Late Write. • Byte Write Capability(four byte write selects, one for e.