Document
Integrated Circuit Systems, Inc.
ICS87158
www.DataSheet4U.com 1-TO-6, LVPECL-TO-HCSL/LVCMOS ÷1, ÷2, ÷4 CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS87158 is a high performance 1-to-6 LVPECL-to-HCSL/LVCMOS Clock Generator HiPerClockS™ and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS87158 has one differential input (which can accept LVDS, LVPECL, LVHSTL, SSTL, HCSL), six differential HCSL output pairs and two complementary LVCMOS/LVTTL outputs. The six HCSL output pairs can be individually configured for divide-by-1, 2, and 4 or high impedance by use of select pins. The two complementary LVCMOS/LVTTL outputs can be configured for divide by 2, divide by 4, high impedance, or driven low for low power operation.
FEATURES
• Six HCSL outputs • Two LVCMOS/LVTTL outputs • One Differential LVPECL clock input pair • PCLK, nPCLK supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL • Maximum output frequency: 600MHz (maximum) • Output skew: 100ps (maximum) • Propagation delay: 4ns (maximum) • 3.3V operating supply • 0°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages • Industrial temperature information available upon request
IC S
The primary use of the ICS87158 is in Intel ® E8870 chipsets that use Intel ® Pentium 4 processors. The ICS87158 converts the differential clock from the main system clock into HCSL clocks used by Intel ® Pentium 4 processors. However, the ICS87158 is a highly flexible, general purpose device that operates up to 600MHz and can be used in any situation where Differential-to-HCSL translation is required.
BLOCK DIAGRAM
MULT_0 MULT_1 IREF
▲
PIN ASSIGNMENT
GND VDD VDD _R PCLK nPCLK GND_R VDD _M MREF nMREF GND_M VDD GND VDD _L VDD GND_L SEL_T MULT_0 MULT_1 VDD _L GND_L SEL_A SEL_B SEL_U PWR_DWN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD GND_H VDD _H HOST_P1 HOST_N1 GND_H HOST_P2 HOST_N2 VDD _H HOST_P3 HOST_N3 GND_H HOST_P4 HOST_N4 VDD _H HOST_P5 HOST_N5 GND_H HOST_P6 HOST_N6 VDD _H IREF GND_I VDD_I
CURRENT ADJUST
+ ÷1,2,4
PWR_DWN# SEL_T
VDD HOST_P1 HOST_N1 GND_H VDD HOST_P6 HOST_N6 GND_H VDD HOST_P2 HOST_N2 GND_H VDD HOST_P3 HOST_N3 GND_H VDD HOST_P4 HOST_N4 GND_H VDD HOST_P5 HOST_N5 GND_H VDD MREF nMREF GND_H
PCLK nPCLK
÷1,2,4
SEL_A SEL_B SEL_U
DIVIDER CONTROL
48-Lead TSSOP 6.1mm x 12.5mm x .92mm body package G Package Top View 48-Lead SSOP 7.5mm x 15.9mm x 2.3mm body package F Package Top View
REV. B JANUARY 17, 2006
÷2,4
87158AG
www.icst.com/products/hiperclocks.html
1
Integrated Circuit Systems, Inc.
ICS87158
www.DataSheet4U.com 1-TO-6, LVPECL-TO-HCSL/LVCMOS ÷1, ÷2, ÷4 CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number 1, 12 2, 11, 14, 48 3 4 5 6 7 8, 9 10 13 15, 20 16 17 Name GND VDD VDD_R PCLK nPCLK GND_R VDD_M MREF, nMREF GND_M VDD_L GND_L SEL_T MULT_0 Type Power Power Power Input Input Power Power Output Power Power Power Input Input Description Power supply ground. Positive supply pins. Power supply pin for differential reference clock inputs. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Power supply ground for differential inputs. Power supply pin for MREF clock outputs. Single ended clocks provided as a reference clock to a memor y clock driver. LVCMOS / LVTTL interface levels. Power supply ground for MREF clock outputs. Power supply pin for logic input pins. Power supply ground for logic input pins. Active high input tristates all outputs. Pulldown LVCMOS / LVTTL interface levels. The logic setting on these two pins selects the multiplying factor Pulldown of the IREF reference current for the HOST pair outputs. LVCMOS / LVTTL interface levels. The logic setting on these two pins selects the multiplying factor of the IREF reference current for the HOST pair outputs. Pullup LVCMOS / LVTTL interface levels. Power supply pin for logic input pins. Pulldown Selects desired output frequencies. LVCMOS / LVTTL interface levels. Asynchronous active-low LVTTL power-down signal forces MREF outputs low, tristates HOST_N outputs, and drives HOST_P output currents to 2xIREF. LVCMOS / LVTTL interface levels. Power supply pin for IREF current reference input. Power supply ground for IREF current reference input. A fixed precision resistor from this pin to ground provides a reference current used for differential current-mode HOST clock outputs. Power supply pins for the differential HOST clock outputs. Differential output pairs. HCSL interface levels.
18 19 21, 22, 23
MULT_1 VDD_L SEL_A, SEL_B, SEL_U PWR_DWN# VDD_I GND_I IREF VDD_H HOST_N6, HOST_P6
Input Power Input
24 25 26 27 28, 34, 40, 46 29, 30 31, 37, 43, 47
Input Power Power Input Power Output
Pullup
GND_H Power Power supply ground for the differential HOST clock outputs. HOST_N5, 32, 33 Output Differential output pairs. HCSL interface levels. HOST_P5 HOST_N4, Dif.