bits ADC. ADC1006S070 Datasheet

ADC1006S070 ADC. Datasheet pdf. Equivalent

ADC1006S070 Datasheet
Recommendation ADC1006S070 Datasheet
Part ADC1006S070
Description (ADC1006S055 / ADC1006S070) Single 10 bits ADC
Feature ADC1006S070; ADC1006S055/070 Single 10 bits ADC, up to 55 MHz or 70 MHz Rev. 02 — 12 August 2008 www.DataSheet4U.
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Datasheet
Download ADC1006S070 Datasheet




NXP Semiconductors ADC1006S070
ADC1006S055/070
www.DataSheet4U.com
Single 10 bits ADC, up to 55 MHz or 70 MHz
Rev. 02 — 12 August 2008
Product data sheet
1. General description
The ADC1006S055/070 are a family of Bipolar CMOS (BiCMOS) 10-bit Analog-to-Digital
Converters (ADC) optimized for a wide range of applications such as cellular
infrastructures, professional telecommunications, imaging, and digital radio. It converts
the analog input signal into 10-bit binary coded digital words at a maximum sampling rate
of 70 MHz. All static digital inputs (SH, CE and OTC) are Transistor-Transistor Logic (TTL)
and CMOS compatible and all outputs are CMOS compatible. A sine wave clock input
signal can also be used.
2. Features
I 10-bit resolution
I Sampling rate up to 70 MHz
I 3 dB bandwidth of 245 MHz
I 5 V power supplies and 3.3 V output power supply
I Binary or two’s complement CMOS outputs
I In-range CMOS compatible output
I TTL and CMOS compatible static digital inputs
I TTL and CMOS compatible digital outputs
I Differential AC or Positive Emitter-Coupled Logic (PECL) clock input; TTL compatible
I Power dissipation 550 mW (typical)
I Low analog input capacitance (typical 2 pF), no buffer amplifier required
I Integrated sample-and-hold amplifier
I Differential analog input
I External amplitude range control
I Voltage controlled regulator included
I 40 °C to +85 °C ambient temperature
3. Applications
High-speed analog-to-digital conversion for:
I Cellular infrastructure
I Professional telecommunication
I Digital radio
I Radar
I Medical imaging
I Fixed network
I Cable modem



NXP Semiconductors ADC1006S070
NXP Semiconductors
ADC1006S055/070
www.DataSheet4U.com
Single 10 bits ADC, up to 55 MHz or 70 MHz
I Barcode scanner
I Cable Modem Termination System (CMTS)/Data Over Cable Service Interface
Specification (DOCSIS)
4. Quick reference data
Table 1. Quick reference data
VCCA = V2 to V44, V3 to V4 and V41 to V40 = 4.75 V to 5.25 V; VCCD = V37 to V38 and
V15 to V17 = 4.75 V to 5.25 V; VCCO = V33 to V34 = 3.0 V to 3.6 V; AGND and DGND shorted
together; Tamb = 40 °C to +85 °C; VI(IN)(p-p) VI(INN)(p-p) = 1.9 V; VVREF = VCCA3 1.75 V;
VI(cm) = VCCA3 1.6 V; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V,
Tamb = 25 °C and CL = 10 pF; unless otherwise specified.
Symbol Parameter
Conditions
Min Typ Max Unit
VCCA
VCCD
VCCO
ICCA
ICCD
ICCO
INL
DNL
analog supply voltage
digital supply voltage
output supply voltage
analog supply current
digital supply current
output supply current
integral non-linearity
differential non-linearity
fclk = 20 MHz;
fi = 400 kHz
fclk = 20 MHz;
fi = 400 kHz
fclk = 20 MHz;
fi = 400 kHz
(no missing code
guaranteed)
4.75 5.0
4.75 5.0
3.0 3.3
- 78
- 27
-3
5.25 V
5.25 V
3.6 V
87 mA
30 mA
4 mA
- ±0.65 ±1.12 LSB
- ±0.12 ±0.27 LSB
fclk(max)
maximum clock
frequency
ADC1006S055H 55 - - MHz
ADC1006S070H 70 - - MHz
Ptot total power dissipation fclk = 55 MHz;
fi = 20 MHz
- 550 660 mW
5. Ordering information
Table 2. Ordering information
Type number
Package
Name
Description
ADC1006S055H QFP44
ADC1006S070H QFP44
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 × 10 × 1.75 mm
Version
Sampling
frequency
(MHz)
SOT307-2 55
SOT307-2 70
ADC1006S055_070_2
Product data sheet
Rev. 02 — 12 August 2008
© NXP B.V. 2008. All rights reserved.
2 of 31



NXP Semiconductors ADC1006S070
NXP Semiconductors
6. Block diagram
ADC1006S055/070
www.DataSheet4U.com
Single 10 bits ADC, up to 55 MHz or 70 MHz
VCCA1 VCCA3 VCCA4 CLKN CLK
VCCD1 VCCD2 OTC CE
2 3 41
35 36
37 15 18 19
n.c.
FSREF
VREF
sample -
and - hold
INN
IN
SH
6 to 10, 13,
14, 16, 31, 32
12 VREF
REFERENCE
11
AMP
CLOCK DRIVER
43
ANALOG-TO-DIGITAL
CONVERTER
LATCHES
42
s
39
1
CMADC
5
DEC
CMADC
REFERENCE
ADC1006S055/070
OVERFLOW/
UNDERFLOW
LATCH
21 D9
22 D8
23 D7
24 D6
CMOS
OUTPUTS
25 D5
26 D4
27 D3
28 D2
29 D1
30 D0
MSB
data
outputs
LSB
33 VCCO
CMOS 20
OUTPUT
IR
44 4 40 38 17
34
AGND1
AGND3 AGND4
Fig 1. Block diagram
DGND1 DGND2
OGND
014aaa464
ADC1006S055_070_2
Product data sheet
Rev. 02 — 12 August 2008
© NXP B.V. 2008. All rights reserved.
3 of 31







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