12-bit ADC. ADC1213D Datasheet

ADC1213D ADC. Datasheet pdf. Equivalent

ADC1213D Datasheet
Recommendation ADC1213D Datasheet
Part ADC1213D
Description Dual 12-bit ADC
Feature ADC1213D; ADC1213D series Rev. 05 — 23 April 2010 www.DataSheet4U.com Dual 12-bit ADC; 65 Msps, 80 Msps, 105.
Manufacture NXP Semiconductors
Datasheet
Download ADC1213D Datasheet




NXP Semiconductors ADC1213D
ADC1213D series
www.DataSheet4U.com
Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps
Rev. 05 — 23 April 2010
Preliminary data sheet
1. General description
The ADC1213D is a dual-channel 12-bit Analog-to-Digital Converter (ADC) optimized for
high dynamic performances and low power at sample rates up to 125 Msps. Pipelined
architecture and output error correction ensure the ADC1213D is accurate enough to
guarantee zero missing codes over the entire operating range. Supplied from a 3 V
source for analog and a 1.8 V source for the output driver, it embeds two serial outputs.
Each lane is differential and complies with the JESD204A standard. An integrated Serial
Peripheral Interface (SPI) allows the user to easily configure the ADC. A set of IC
configurations is also available via the binary level control pins taken, which are used at
power-up. The device also includes a SPI programmable full-scale to allow flexible input
voltage range from 1 V to 2 V (peak-to-peak).
Excellent dynamic performance is maintained from the baseband to input frequencies of
170 MHz or more, making the ADC1213D ideal for use in communications, imaging, and
medical applications.
2. Features and benefits
„ SNR, 70 dBFS; SFDR, 86 dBc
„ Sample rate up to 125 Msps
„ Clock input divider by 2 for less jitter
contribution
„ 3 V, 1.8 V single supplies
„ Flexible input voltage range:
1 V to 2 V (peak-to-peak)
„ Two configurable serial outputs
„ INL ± 1 LSB; DNL ± 0.5 LSB
„ Pin compatible with the ADC1213D
series
„ HVQFN56 package
„ Input bandwidth, 600 MHz
„ Power dissipation, 995 mW at 80 Msps
„ SPI register programming
„ Duty cycle stabilizer
„ High IF capability
„ Offset binary, two’s complement, gray
code
„ Power-down mode and Sleep mode
„ Compliant with JESD204A serial
transmission standard
3. Applications
„ Wireless and wired broadband
communications
„ Spectral analysis
„ Ultrasound equipment
„ Portable instrumentation
„ Imaging systems
„ Software defined radio



NXP Semiconductors ADC1213D
NXP Semiconductors
ADC1213D series
www.DataSheet4U.com
ADC1213D series
4. Ordering information
Table 1. Ordering information
Type number
Sampling
frequency
(Msps)
ADC1213D125HN/C1 125
ADC1213D105HN/C1 105
ADC1213D080HN/C1 80
ADC1213D065HN/C1 65
5. Block diagram
Package
Name
Description
Version
HVQFN56
HVQFN56
HVQFN56
HVQFN56
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
plastic thermal enhanced very thin quad flat package; SOT684-7
no leads; 56 terminals; body 8 × 8 × 0.85 mm
INAP
INAM
T/H
INPUT
STAGE
CLKP
CLKM
DLL
PLL
INBP
INBM
T/H
INPUT
STAGE
ADC1213D
Fig 1. Block diagram
CFG (0 to 3) SDIO/DCS
SCLK/DCS
CS
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADCA CORE
12-BIT
PIPELINED
D11 to D0
OTR
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SPI
8-bit
8-bit
SYNCP
SYNCN
SWING_n
10-bit
SERIALIZER A
OUTPUT
BUFFER A
CMLPA
CMLNA
ERROR
CORRECTION AND
DIGITAL
PROCESSING
ADCB CORE
12-BIT
PIPELINED
OTR
D11 to D0
8-bit
8-bit
10-bit
SERIALIZER B
OUTPUT
BUFFER B
CMLPB
CMLNB
SWING_n
CLOCK INPUT
STAGE & DUTY
CYCLE CONTROL
SYSTEM
REFERENCE AND
POWER
MANAGEMENT
SCRAMBLER RESET
REFBT
REFBB
VCMB
SENSE
REFAB
REFAT
VCMA
VREF
005aaa120
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
2 of 41



NXP Semiconductors ADC1213D
NXP Semiconductors
6. Pinning information
6.1 Pinning
ADC1213D series
www.DataSheet4U.com
ADC1213D series
INAP 1
INAM 2
VCMA 3
REFAT 4
REFAB 5
AGND 6
CLKP 7
CLKN 8
AGND 9
REFBB 10
REFBT 11
VCMB 12
INBM 13
INBP 14
ADC1213D
42 DGND
41 DGND
40 VDDD
39 CMLPA
38 CMLNA
37 VDDD
36 DGND
35 DGND
34 VDDD
33 CMLNB
32 CMLPB
31 VDDD
30 DGND
29 DGND
005aaa121
Fig 2. Pinning diagram
Transparent top view
6.2 Pin description
Table 2.
Symbol
INAP
INAM
VCMA
REFAT
REFAB
AGND
CLKP
CLKM
AGND
REFBB
REFBT
VCMB
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
Type [1]
I
I
O
O
O
G
I
I
G
O
O
O
Description
channel A analog input
channel A complementary analog input
channel A output common voltage
channel A top reference
channel A bottom reference
analog ground
clock input
complementary clock input
analog ground
channel B bottom reference
channel B top reference
channel B output common voltage
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
3 of 41







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